cfee2139a0
* TriCore Support python sample * Update sample_tricore.py Correct attribution * Update sample_tricore.py Fixed byte code to execute properly. * Update sample_tricore.py Removed testing artifact * Added tricore msvc config-file.h * Added STATIC to tricore config and added helper methods to symbol file generation. * Update op_helper.c Use built in crc32 * Fix tricore samples and small code blocks are now handled properly * Add CPU types * Generate bindings * Format code Co-authored-by: lazymio <mio@lazym.io>
174 lines
3.9 KiB
C
174 lines
3.9 KiB
C
/* This file is released under LGPL2.
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See COPYING.LGPL2 in root directory for more details
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*/
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/*
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Created for Unicorn Engine by Eric Poole <eric.poole@aptiv.com>, 2022
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Copyright 2022 Aptiv
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*/
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#ifndef UNICORN_TRICORE_H
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#define UNICORN_TRICORE_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _MSC_VER
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#pragma warning(disable : 4201)
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#endif
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//> TRICORE CPU
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typedef enum uc_cpu_tricore {
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UC_CPU_TRICORE_TC1796,
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UC_CPU_TRICORE_TC1797,
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UC_CPU_TRICORE_TC27X,
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UC_CPU_TRICORE_ENDING
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} uc_cpu_tricore;
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//> TRICORE registers
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typedef enum uc_tricore_reg {
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UC_TRICORE_REG_INVALID = 0,
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// General purpose registers (GPR)
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// Address GPR
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UC_TRICORE_REG_A0,
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UC_TRICORE_REG_A1,
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UC_TRICORE_REG_A2,
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UC_TRICORE_REG_A3,
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UC_TRICORE_REG_A4,
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UC_TRICORE_REG_A5,
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UC_TRICORE_REG_A6,
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UC_TRICORE_REG_A7,
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UC_TRICORE_REG_A8,
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UC_TRICORE_REG_A9,
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UC_TRICORE_REG_A10,
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UC_TRICORE_REG_A11,
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UC_TRICORE_REG_A12,
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UC_TRICORE_REG_A13,
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UC_TRICORE_REG_A14,
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UC_TRICORE_REG_A15,
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// Data GPR
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UC_TRICORE_REG_D0,
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UC_TRICORE_REG_D1,
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UC_TRICORE_REG_D2,
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UC_TRICORE_REG_D3,
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UC_TRICORE_REG_D4,
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UC_TRICORE_REG_D5,
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UC_TRICORE_REG_D6,
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UC_TRICORE_REG_D7,
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UC_TRICORE_REG_D8,
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UC_TRICORE_REG_D9,
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UC_TRICORE_REG_D10,
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UC_TRICORE_REG_D11,
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UC_TRICORE_REG_D12,
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UC_TRICORE_REG_D13,
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UC_TRICORE_REG_D14,
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UC_TRICORE_REG_D15,
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/* CSFR Register */
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UC_TRICORE_REG_PCXI,
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UC_TRICORE_REG_PSW,
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/* PSW flag cache for faster execution */
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UC_TRICORE_REG_PSW_USB_C,
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UC_TRICORE_REG_PSW_USB_V,
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UC_TRICORE_REG_PSW_USB_SV,
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UC_TRICORE_REG_PSW_USB_AV,
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UC_TRICORE_REG_PSW_USB_SAV,
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UC_TRICORE_REG_PC,
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UC_TRICORE_REG_SYSCON,
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UC_TRICORE_REG_CPU_ID,
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UC_TRICORE_REG_BIV,
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UC_TRICORE_REG_BTV,
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UC_TRICORE_REG_ISP,
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UC_TRICORE_REG_ICR,
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UC_TRICORE_REG_FCX,
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UC_TRICORE_REG_LCX,
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UC_TRICORE_REG_COMPAT,
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UC_TRICORE_REG_DPR0_U,
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UC_TRICORE_REG_DPR1_U,
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UC_TRICORE_REG_DPR2_U,
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UC_TRICORE_REG_DPR3_U,
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UC_TRICORE_REG_DPR0_L,
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UC_TRICORE_REG_DPR1_L,
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UC_TRICORE_REG_DPR2_L,
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UC_TRICORE_REG_DPR3_L,
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UC_TRICORE_REG_CPR0_U,
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UC_TRICORE_REG_CPR1_U,
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UC_TRICORE_REG_CPR2_U,
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UC_TRICORE_REG_CPR3_U,
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UC_TRICORE_REG_CPR0_L,
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UC_TRICORE_REG_CPR1_L,
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UC_TRICORE_REG_CPR2_L,
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UC_TRICORE_REG_CPR3_L,
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UC_TRICORE_REG_DPM0,
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UC_TRICORE_REG_DPM1,
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UC_TRICORE_REG_DPM2,
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UC_TRICORE_REG_DPM3,
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UC_TRICORE_REG_CPM0,
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UC_TRICORE_REG_CPM1,
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UC_TRICORE_REG_CPM2,
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UC_TRICORE_REG_CPM3,
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/* Memory Management Registers */
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UC_TRICORE_REG_MMU_CON,
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UC_TRICORE_REG_MMU_ASI,
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UC_TRICORE_REG_MMU_TVA,
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UC_TRICORE_REG_MMU_TPA,
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UC_TRICORE_REG_MMU_TPX,
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UC_TRICORE_REG_MMU_TFA,
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// 1.3.1 Only
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UC_TRICORE_REG_BMACON,
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UC_TRICORE_REG_SMACON,
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UC_TRICORE_REG_DIEAR,
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UC_TRICORE_REG_DIETR,
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UC_TRICORE_REG_CCDIER,
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UC_TRICORE_REG_MIECON,
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UC_TRICORE_REG_PIEAR,
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UC_TRICORE_REG_PIETR,
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UC_TRICORE_REG_CCPIER,
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/* Debug Registers */
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UC_TRICORE_REG_DBGSR,
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UC_TRICORE_REG_EXEVT,
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UC_TRICORE_REG_CREVT,
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UC_TRICORE_REG_SWEVT,
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UC_TRICORE_REG_TR0EVT,
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UC_TRICORE_REG_TR1EVT,
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UC_TRICORE_REG_DMS,
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UC_TRICORE_REG_DCX,
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UC_TRICORE_REG_DBGTCR,
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UC_TRICORE_REG_CCTRL,
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UC_TRICORE_REG_CCNT,
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UC_TRICORE_REG_ICNT,
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UC_TRICORE_REG_M1CNT,
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UC_TRICORE_REG_M2CNT,
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UC_TRICORE_REG_M3CNT,
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UC_TRICORE_REG_ENDING, // <-- mark the end of the list of registers
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// alias registers
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UC_TRICORE_REG_GA0 = UC_TRICORE_REG_A0,
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UC_TRICORE_REG_GA1 = UC_TRICORE_REG_A1,
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UC_TRICORE_REG_GA8 = UC_TRICORE_REG_A8,
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UC_TRICORE_REG_GA9 = UC_TRICORE_REG_A9,
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UC_TRICORE_REG_SP = UC_TRICORE_REG_A10,
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UC_TRICORE_REG_LR = UC_TRICORE_REG_A11,
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UC_TRICORE_REG_IA = UC_TRICORE_REG_A15,
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UC_TRICORE_REG_ID = UC_TRICORE_REG_D15,
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} uc_tricore_reg;
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#ifdef __cplusplus
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}
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#endif
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#endif |