159 lines
2.9 KiB
Rust
159 lines
2.9 KiB
Rust
#![allow(non_camel_case_types)]
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// TRICORE registers
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#[repr(C)]
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#[derive(PartialEq, Debug, Clone, Copy)]
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pub enum RegisterTRICORE {
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INVALID = 0,
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A0 = 1,
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A1 = 2,
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A2 = 3,
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A3 = 4,
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A4 = 5,
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A5 = 6,
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A6 = 7,
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A7 = 8,
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A8 = 9,
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A9 = 10,
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A10 = 11,
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A11 = 12,
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A12 = 13,
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A13 = 14,
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A14 = 15,
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A15 = 16,
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D0 = 17,
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D1 = 18,
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D2 = 19,
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D3 = 20,
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D4 = 21,
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D5 = 22,
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D6 = 23,
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D7 = 24,
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D8 = 25,
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D9 = 26,
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D10 = 27,
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D11 = 28,
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D12 = 29,
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D13 = 30,
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D14 = 31,
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D15 = 32,
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PCXI = 33,
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PSW = 34,
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PSW_USB_C = 35,
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PSW_USB_V = 36,
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PSW_USB_SV = 37,
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PSW_USB_AV = 38,
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PSW_USB_SAV = 39,
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PC = 40,
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SYSCON = 41,
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CPU_ID = 42,
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BIV = 43,
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BTV = 44,
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ISP = 45,
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ICR = 46,
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FCX = 47,
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LCX = 48,
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COMPAT = 49,
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DPR0_U = 50,
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DPR1_U = 51,
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DPR2_U = 52,
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DPR3_U = 53,
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DPR0_L = 54,
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DPR1_L = 55,
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DPR2_L = 56,
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DPR3_L = 57,
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CPR0_U = 58,
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CPR1_U = 59,
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CPR2_U = 60,
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CPR3_U = 61,
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CPR0_L = 62,
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CPR1_L = 63,
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CPR2_L = 64,
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CPR3_L = 65,
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DPM0 = 66,
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DPM1 = 67,
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DPM2 = 68,
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DPM3 = 69,
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CPM0 = 70,
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CPM1 = 71,
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CPM2 = 72,
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CPM3 = 73,
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MMU_CON = 74,
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MMU_ASI = 75,
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MMU_TVA = 76,
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MMU_TPA = 77,
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MMU_TPX = 78,
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MMU_TFA = 79,
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BMACON = 80,
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SMACON = 81,
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DIEAR = 82,
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DIETR = 83,
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CCDIER = 84,
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MIECON = 85,
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PIEAR = 86,
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PIETR = 87,
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CCPIER = 88,
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DBGSR = 89,
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EXEVT = 90,
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CREVT = 91,
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SWEVT = 92,
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TR0EVT = 93,
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TR1EVT = 94,
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DMS = 95,
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DCX = 96,
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DBGTCR = 97,
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CCTRL = 98,
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CCNT = 99,
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ICNT = 100,
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M1CNT = 101,
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M2CNT = 102,
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M3CNT = 103,
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ENDING = 104,
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}
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impl RegisterTRICORE {
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// alias registers
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// (assoc) GA0 = 1,
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// (assoc) GA1 = 2,
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// (assoc) GA8 = 9,
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// (assoc) GA9 = 10,
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// (assoc) SP = 11,
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// (assoc) LR = 12,
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// (assoc) IA = 16,
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// (assoc) ID = 32,
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pub const GA0: RegisterTRICORE = RegisterTRICORE::A0;
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pub const GA1: RegisterTRICORE = RegisterTRICORE::A1;
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pub const GA8: RegisterTRICORE = RegisterTRICORE::A8;
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pub const GA9: RegisterTRICORE = RegisterTRICORE::A9;
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pub const SP: RegisterTRICORE = RegisterTRICORE::A10;
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pub const LR: RegisterTRICORE = RegisterTRICORE::A11;
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pub const IA: RegisterTRICORE = RegisterTRICORE::A15;
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pub const ID: RegisterTRICORE = RegisterTRICORE::D15;
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}
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impl From<RegisterTRICORE> for i32 {
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fn from(r: RegisterTRICORE) -> Self {
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r as i32
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}
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}
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#[repr(i32)]
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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pub enum TricoreCpuModel {
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UC_CPU_TRICORE_TC1796,
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UC_CPU_TRICORE_TC1797,
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UC_CPU_TRICORE_TC27X,
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}
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impl From<TricoreCpuModel> for i32 {
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fn from(value: TricoreCpuModel) -> Self {
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value as i32
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}
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}
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impl From<&TricoreCpuModel> for i32 {
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fn from(value: &TricoreCpuModel) -> Self {
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(*value) as i32
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}
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}
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