229 lines
7.4 KiB
C
229 lines
7.4 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
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#include "uc_priv.h"
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#include "sysemu/cpus.h"
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#include "cpu.h"
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#include "unicorn_common.h"
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#include "cpu_bits.h"
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#include <unicorn/riscv.h>
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#include "unicorn.h"
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static int csrno_map[] = {
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CSR_USTATUS, CSR_UIE, CSR_UTVEC, CSR_USCRATCH,
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CSR_UEPC, CSR_UCAUSE, CSR_UTVAL, CSR_UIP,
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CSR_FFLAGS, CSR_FRM, CSR_FCSR, CSR_CYCLE,
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CSR_TIME, CSR_INSTRET, CSR_HPMCOUNTER3, CSR_HPMCOUNTER4,
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CSR_HPMCOUNTER5, CSR_HPMCOUNTER6, CSR_HPMCOUNTER7, CSR_HPMCOUNTER8,
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CSR_HPMCOUNTER9, CSR_HPMCOUNTER10, CSR_HPMCOUNTER11, CSR_HPMCOUNTER12,
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CSR_HPMCOUNTER13, CSR_HPMCOUNTER14, CSR_HPMCOUNTER15, CSR_HPMCOUNTER16,
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CSR_HPMCOUNTER17, CSR_HPMCOUNTER18, CSR_HPMCOUNTER19, CSR_HPMCOUNTER20,
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CSR_HPMCOUNTER21, CSR_HPMCOUNTER22, CSR_HPMCOUNTER23, CSR_HPMCOUNTER24,
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CSR_HPMCOUNTER25, CSR_HPMCOUNTER26, CSR_HPMCOUNTER27, CSR_HPMCOUNTER28,
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CSR_HPMCOUNTER29, CSR_HPMCOUNTER30, CSR_HPMCOUNTER31, CSR_CYCLEH,
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CSR_TIMEH, CSR_INSTRETH, CSR_HPMCOUNTER3H, CSR_HPMCOUNTER4H,
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CSR_HPMCOUNTER5H, CSR_HPMCOUNTER6H, CSR_HPMCOUNTER7H, CSR_HPMCOUNTER8H,
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CSR_HPMCOUNTER9H, CSR_HPMCOUNTER10H, CSR_HPMCOUNTER11H, CSR_HPMCOUNTER12H,
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CSR_HPMCOUNTER13H, CSR_HPMCOUNTER14H, CSR_HPMCOUNTER15H, CSR_HPMCOUNTER16H,
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CSR_HPMCOUNTER17H, CSR_HPMCOUNTER18H, CSR_HPMCOUNTER19H, CSR_HPMCOUNTER20H,
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CSR_HPMCOUNTER21H, CSR_HPMCOUNTER22H, CSR_HPMCOUNTER23H, CSR_HPMCOUNTER24H,
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CSR_HPMCOUNTER25H, CSR_HPMCOUNTER26H, CSR_HPMCOUNTER27H, CSR_HPMCOUNTER28H,
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CSR_HPMCOUNTER29H, CSR_HPMCOUNTER30H, CSR_HPMCOUNTER31H, CSR_MCYCLE,
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CSR_MINSTRET, CSR_MCYCLEH, CSR_MINSTRETH, CSR_MVENDORID,
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CSR_MARCHID, CSR_MIMPID, CSR_MHARTID, CSR_MSTATUS,
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CSR_MISA, CSR_MEDELEG, CSR_MIDELEG, CSR_MIE,
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CSR_MTVEC, CSR_MCOUNTEREN, CSR_MSTATUSH, CSR_MUCOUNTEREN,
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CSR_MSCOUNTEREN, CSR_MHCOUNTEREN, CSR_MSCRATCH, CSR_MEPC,
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CSR_MCAUSE, CSR_MTVAL, CSR_MIP, CSR_MBADADDR,
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CSR_SSTATUS, CSR_SEDELEG, CSR_SIDELEG, CSR_SIE,
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CSR_STVEC, CSR_SCOUNTEREN, CSR_SSCRATCH, CSR_SEPC,
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CSR_SCAUSE, CSR_STVAL, CSR_SIP, CSR_SBADADDR,
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CSR_SPTBR, CSR_SATP, CSR_HSTATUS, CSR_HEDELEG,
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CSR_HIDELEG, CSR_HIE, CSR_HCOUNTEREN, CSR_HTVAL,
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CSR_HIP, CSR_HTINST, CSR_HGATP, CSR_HTIMEDELTA,
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CSR_HTIMEDELTAH,
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};
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#define csrno_count (sizeof(csrno_map) / sizeof(int))
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RISCVCPU *cpu_riscv_init(struct uc_struct *uc);
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static void riscv_set_pc(struct uc_struct *uc, uint64_t address)
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{
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RISCV_CPU(uc->cpu)->env.pc = address;
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}
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static uint64_t riscv_get_pc(struct uc_struct *uc)
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{
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return RISCV_CPU(uc->cpu)->env.pc;
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}
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static void riscv_release(void *ctx)
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{
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int i;
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TCGContext *tcg_ctx = (TCGContext *)ctx;
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RISCVCPU *cpu = (RISCVCPU *)tcg_ctx->uc->cpu;
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CPUTLBDesc *d = cpu->neg.tlb.d;
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CPUTLBDescFast *f = cpu->neg.tlb.f;
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CPUTLBDesc *desc;
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CPUTLBDescFast *fast;
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release_common(ctx);
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for (i = 0; i < NB_MMU_MODES; i++) {
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desc = &(d[i]);
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fast = &(f[i]);
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g_free(desc->iotlb);
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g_free(fast->table);
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}
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}
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static void reg_reset(struct uc_struct *uc) {}
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DEFAULT_VISIBILITY
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uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
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size_t *size)
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{
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CPURISCVState *env = _env;
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uc_err ret = UC_ERR_ARG;
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if (regid >= UC_RISCV_REG_X0 && regid <= UC_RISCV_REG_X31) {
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#ifdef TARGET_RISCV64
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CHECK_REG_TYPE(uint64_t);
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*(uint64_t *)value = env->gpr[regid - UC_RISCV_REG_X0];
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#else
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->gpr[regid - UC_RISCV_REG_X0];
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#endif
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} else if (regid >= UC_RISCV_REG_F0 &&
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regid <= UC_RISCV_REG_F31) { // "ft0".."ft31"
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CHECK_REG_TYPE(uint64_t);
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*(uint64_t *)value = env->fpr[regid - UC_RISCV_REG_F0];
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} else if (regid >= UC_RISCV_REG_USTATUS &&
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regid < UC_RISCV_REG_USTATUS + csrno_count) {
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target_ulong val;
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int csrno = csrno_map[regid - UC_RISCV_REG_USTATUS];
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riscv_csrrw(env, csrno, &val, -1, 0);
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#ifdef TARGET_RISCV64
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CHECK_REG_TYPE(uint64_t);
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*(uint64_t *)value = (uint64_t)val;
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#else
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = (uint32_t)val;
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#endif
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} else {
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switch (regid) {
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default:
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break;
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case UC_RISCV_REG_PC:
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#ifdef TARGET_RISCV64
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CHECK_REG_TYPE(uint64_t);
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*(uint64_t *)value = env->pc;
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#else
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->pc;
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#endif
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break;
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}
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}
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return ret;
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}
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DEFAULT_VISIBILITY
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uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
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size_t *size, int *setpc)
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{
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CPURISCVState *env = _env;
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uc_err ret = UC_ERR_ARG;
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if (regid >= UC_RISCV_REG_X0 && regid <= UC_RISCV_REG_X31) {
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#ifdef TARGET_RISCV64
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CHECK_REG_TYPE(uint64_t);
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env->gpr[regid - UC_RISCV_REG_X0] = *(uint64_t *)value;
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#else
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CHECK_REG_TYPE(uint32_t);
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env->gpr[regid - UC_RISCV_REG_X0] = *(uint32_t *)value;
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#endif
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} else if (regid >= UC_RISCV_REG_F0 &&
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regid <= UC_RISCV_REG_F31) { // "ft0".."ft31"
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CHECK_REG_TYPE(uint64_t);
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env->fpr[regid - UC_RISCV_REG_F0] = *(uint64_t *)value;
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} else if (regid >= UC_RISCV_REG_USTATUS &&
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regid < UC_RISCV_REG_USTATUS + csrno_count) {
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target_ulong val;
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int csrno = csrno_map[regid - UC_RISCV_REG_USTATUS];
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#ifdef TARGET_RISCV64
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CHECK_REG_TYPE(uint64_t);
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riscv_csrrw(env, csrno, &val, *(uint64_t *)value, -1);
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#else
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CHECK_REG_TYPE(uint32_t);
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riscv_csrrw(env, csrno, &val, *(uint32_t *)value, -1);
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#endif
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} else {
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switch (regid) {
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default:
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break;
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case UC_RISCV_REG_PC:
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#ifdef TARGET_RISCV64
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CHECK_REG_TYPE(uint64_t);
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env->pc = *(uint64_t *)value;
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#else
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CHECK_REG_TYPE(uint32_t);
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env->pc = *(uint32_t *)value;
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#endif
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*setpc = 1;
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break;
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}
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}
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return ret;
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}
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static bool riscv_stop_interrupt(struct uc_struct *uc, int intno)
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{
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// detect stop exception
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switch (intno) {
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default:
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return false;
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case RISCV_EXCP_UNICORN_END:
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return true;
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case RISCV_EXCP_BREAKPOINT:
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uc->invalid_error = UC_ERR_EXCEPTION;
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return true;
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}
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}
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static bool riscv_insn_hook_validate(uint32_t insn_enum)
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{
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return false;
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}
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static int riscv_cpus_init(struct uc_struct *uc, const char *cpu_model)
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{
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RISCVCPU *cpu;
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cpu = cpu_riscv_init(uc);
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if (cpu == NULL) {
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return -1;
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}
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return 0;
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}
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DEFAULT_VISIBILITY
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void uc_init(struct uc_struct *uc)
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{
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uc->reg_read = reg_read;
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uc->reg_write = reg_write;
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uc->reg_reset = reg_reset;
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uc->release = riscv_release;
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uc->set_pc = riscv_set_pc;
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uc->get_pc = riscv_get_pc;
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uc->stop_interrupt = riscv_stop_interrupt;
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uc->insn_hook_validate = riscv_insn_hook_validate;
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uc->cpus_init = riscv_cpus_init;
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uc->cpu_context_size = offsetof(CPURISCVState, rdtime_fn);
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uc_common_init(uc);
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}
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