4055a5ab10
These APIs take size parameters, which can be used to properly bounds-check the inputs and outputs for various registers. Additionally, all backends now throw UC_ERR_ARG if the input register numbers are invalid. Completes #1831.
301 lines
8.3 KiB
C
301 lines
8.3 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
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#include "sysemu/cpus.h"
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#include "cpu.h"
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#include "unicorn_common.h"
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#include "uc_priv.h"
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#include "unicorn.h"
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#include "internal.h"
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#ifdef TARGET_MIPS64
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typedef uint64_t mipsreg_t;
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#else
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typedef uint32_t mipsreg_t;
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#endif
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MIPSCPU *cpu_mips_init(struct uc_struct *uc);
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static void mips_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUMIPSState *)uc->cpu->env_ptr)->active_tc.PC = address;
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}
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static uint64_t mips_get_pc(struct uc_struct *uc)
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{
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return ((CPUMIPSState *)uc->cpu->env_ptr)->active_tc.PC;
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}
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static void mips_release(void *ctx)
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{
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int i;
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TCGContext *tcg_ctx = (TCGContext *)ctx;
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MIPSCPU *cpu = (MIPSCPU *)tcg_ctx->uc->cpu;
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CPUTLBDesc *d = cpu->neg.tlb.d;
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CPUTLBDescFast *f = cpu->neg.tlb.f;
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CPUTLBDesc *desc;
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CPUTLBDescFast *fast;
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release_common(ctx);
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for (i = 0; i < NB_MMU_MODES; i++) {
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desc = &(d[i]);
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fast = &(f[i]);
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g_free(desc->iotlb);
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g_free(fast->table);
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}
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g_free(cpu->env.mvp);
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g_free(cpu->env.tlb);
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}
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void mips_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env;
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(void)uc;
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env = uc->cpu->env_ptr;
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memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr));
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env->active_tc.PC = 0;
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}
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static uc_err reg_read(CPUMIPSState *env, unsigned int regid, void *value,
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size_t *size)
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{
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uc_err ret = UC_ERR_ARG;
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31) {
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CHECK_REG_TYPE(mipsreg_t);
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*(mipsreg_t *)value = env->active_tc.gpr[regid - UC_MIPS_REG_0];
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} else {
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switch (regid) {
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default:
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break;
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case UC_MIPS_REG_HI:
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CHECK_REG_TYPE(mipsreg_t);
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*(mipsreg_t *)value = env->active_tc.HI[0];
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break;
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case UC_MIPS_REG_LO:
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CHECK_REG_TYPE(mipsreg_t);
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*(mipsreg_t *)value = env->active_tc.LO[0];
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break;
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case UC_MIPS_REG_PC:
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CHECK_REG_TYPE(mipsreg_t);
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*(mipsreg_t *)value = env->active_tc.PC;
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break;
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case UC_MIPS_REG_CP0_CONFIG3:
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CHECK_REG_TYPE(mipsreg_t);
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*(mipsreg_t *)value = env->CP0_Config3;
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break;
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case UC_MIPS_REG_CP0_STATUS:
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CHECK_REG_TYPE(mipsreg_t);
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*(mipsreg_t *)value = env->CP0_Status;
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break;
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case UC_MIPS_REG_CP0_USERLOCAL:
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CHECK_REG_TYPE(mipsreg_t);
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*(mipsreg_t *)value = env->active_tc.CP0_UserLocal;
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break;
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}
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}
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return ret;
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}
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static uc_err reg_write(CPUMIPSState *env, unsigned int regid,
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const void *value, size_t *size)
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{
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uc_err ret = UC_ERR_ARG;
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31) {
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CHECK_REG_TYPE(mipsreg_t);
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env->active_tc.gpr[regid - UC_MIPS_REG_0] = *(mipsreg_t *)value;
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} else {
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switch (regid) {
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default:
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break;
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case UC_MIPS_REG_HI:
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CHECK_REG_TYPE(mipsreg_t);
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env->active_tc.HI[0] = *(mipsreg_t *)value;
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break;
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case UC_MIPS_REG_LO:
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CHECK_REG_TYPE(mipsreg_t);
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env->active_tc.LO[0] = *(mipsreg_t *)value;
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break;
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case UC_MIPS_REG_PC:
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CHECK_REG_TYPE(mipsreg_t);
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env->active_tc.PC = *(mipsreg_t *)value;
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break;
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case UC_MIPS_REG_CP0_CONFIG3:
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CHECK_REG_TYPE(mipsreg_t);
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env->CP0_Config3 = *(mipsreg_t *)value;
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break;
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case UC_MIPS_REG_CP0_STATUS:
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// TODO: ALL CP0 REGS
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// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00090-2B-MIPS32PRA-AFP-06.02.pdf
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// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00582-2B-microMIPS32-AFP-05.04.pdf
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CHECK_REG_TYPE(mipsreg_t);
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env->CP0_Status = *(mipsreg_t *)value;
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compute_hflags(env);
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break;
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case UC_MIPS_REG_CP0_USERLOCAL:
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CHECK_REG_TYPE(mipsreg_t);
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env->active_tc.CP0_UserLocal = *(mipsreg_t *)value;
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break;
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}
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}
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return ret;
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}
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int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void *const *vals,
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size_t *sizes, int count)
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{
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CPUMIPSState *env = &(MIPS_CPU(uc->cpu)->env);
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int i;
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uc_err err;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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err = reg_read(env, regid, value, sizes ? sizes + i : NULL);
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if (err) {
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return err;
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}
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}
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return UC_ERR_OK;
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}
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int mips_reg_write(struct uc_struct *uc, unsigned int *regs,
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const void *const *vals, size_t *sizes, int count)
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{
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CPUMIPSState *env = &(MIPS_CPU(uc->cpu)->env);
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int i;
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uc_err err;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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err = reg_write(env, regid, value, sizes ? sizes + i : NULL);
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if (err) {
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return err;
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}
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if (regid == UC_MIPS_REG_PC) {
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// force to quit execution and flush TB
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uc->quit_request = true;
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break_translation_loop(uc);
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}
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}
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return UC_ERR_OK;
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}
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DEFAULT_VISIBILITY
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#ifdef TARGET_MIPS64
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#ifdef TARGET_WORDS_BIGENDIAN
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int mips64_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, size_t *sizes, int count)
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#else
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int mips64el_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, size_t *sizes, int count)
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#endif
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#else // if TARGET_MIPS
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#ifdef TARGET_WORDS_BIGENDIAN
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int mips_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, size_t *sizes, int count)
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#else
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int mipsel_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, size_t *sizes, int count)
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#endif
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#endif
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{
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CPUMIPSState *env = (CPUMIPSState *)ctx->data;
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int i;
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uc_err err;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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err = reg_read(env, regid, value, sizes ? sizes + i : NULL);
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if (err) {
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return err;
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}
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}
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return UC_ERR_OK;
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}
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DEFAULT_VISIBILITY
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#ifdef TARGET_MIPS64
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#ifdef TARGET_WORDS_BIGENDIAN
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int mips64_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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const void *const *vals, size_t *sizes, int count)
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#else
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int mips64el_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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const void *const *vals, size_t *sizes,
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int count)
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#endif
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#else // if TARGET_MIPS
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#ifdef TARGET_WORDS_BIGENDIAN
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int mips_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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const void *const *vals, size_t *sizes, int count)
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#else
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int mipsel_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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const void *const *vals, size_t *sizes, int count)
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#endif
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#endif
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{
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CPUMIPSState *env = (CPUMIPSState *)ctx->data;
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int i;
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uc_err err;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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err = reg_write(env, regid, value, sizes ? sizes + i : NULL);
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if (err) {
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return err;
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}
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}
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return UC_ERR_OK;
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}
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static int mips_cpus_init(struct uc_struct *uc, const char *cpu_model)
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{
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MIPSCPU *cpu;
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cpu = cpu_mips_init(uc);
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if (cpu == NULL) {
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return -1;
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}
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return 0;
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}
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DEFAULT_VISIBILITY
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#ifdef TARGET_MIPS64
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#ifdef TARGET_WORDS_BIGENDIAN
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void mips64_uc_init(struct uc_struct *uc)
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#else
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void mips64el_uc_init(struct uc_struct *uc)
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#endif
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#else // if TARGET_MIPS
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#ifdef TARGET_WORDS_BIGENDIAN
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void mips_uc_init(struct uc_struct *uc)
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#else
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void mipsel_uc_init(struct uc_struct *uc)
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#endif
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#endif
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{
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uc->reg_read = mips_reg_read;
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uc->reg_write = mips_reg_write;
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uc->reg_reset = mips_reg_reset;
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uc->release = mips_release;
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uc->set_pc = mips_set_pc;
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uc->get_pc = mips_get_pc;
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uc->cpus_init = mips_cpus_init;
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uc->cpu_context_size = offsetof(CPUMIPSState, end_reset_fields);
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uc_common_init(uc);
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}
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