aa86641e16
The SR register in the `CPUM68KState` struct does not contain the value of the lower 5 flags. To compute them, we must OR the CCR values with the SR register to get the true SR value.
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
#include "unicorn_test.h"
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const uint64_t code_start = 0x1000;
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const uint64_t code_len = 0x4000;
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static void uc_common_setup(uc_engine **uc, uc_arch arch, uc_mode mode,
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const char *code, uint64_t size,
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uc_cpu_m68k cpu_model)
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{
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OK(uc_open(arch, mode, uc));
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OK(uc_ctl_set_cpu_model(*uc, cpu_model));
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OK(uc_mem_map(*uc, code_start, code_len, UC_PROT_ALL));
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OK(uc_mem_write(*uc, code_start, code, size));
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}
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static void test_move_to_sr(void)
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{
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uc_engine *uc;
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char code[] = "\x46\xfc\x27\x00"; // move #$2700,sr
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int r_sr;
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uc_common_setup(&uc, UC_ARCH_M68K, UC_MODE_BIG_ENDIAN, code,
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sizeof(code) - 1, UC_CPU_M68K_M68000);
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OK(uc_reg_read(uc, UC_M68K_REG_SR, &r_sr));
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r_sr = r_sr | 0x2000;
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OK(uc_reg_write(uc, UC_M68K_REG_SR, &r_sr));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_M68K_REG_SR, &r_sr));
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TEST_CHECK(r_sr == 0x2700);
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OK(uc_close(uc));
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}
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static void test_sr_contains_flags(void)
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{
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uc_engine *uc;
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uint8_t code[] = {
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0x76, 0xed, // moveq #-19, %d3
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};
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uint32_t d3, sr;
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uc_common_setup(&uc, UC_ARCH_M68K, UC_MODE_BIG_ENDIAN, code, sizeof(code),
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UC_CPU_M68K_M68000);
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code), 0, 0));
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OK(uc_reg_read(uc, UC_M68K_REG_D3, &d3));
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OK(uc_reg_read(uc, UC_M68K_REG_SR, &sr));
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TEST_CHECK(d3 == 0xFFFFFFED);
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TEST_CHECK((sr & 0x8) /* N flag */ == 0x8);
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OK(uc_close(uc));
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}
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TEST_LIST = {{"test_move_to_sr", test_move_to_sr},
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{"test_sr_contains_flags", test_sr_contains_flags},
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{NULL, NULL}};
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