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unicorn/bindings/go/unicorn/riscv_const.go
Martin Atkins 7d8fe2ab11 riscv: Expose privilege level as pseudo-register PRIV (#1989) 
Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.

The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.

The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.
2024-11-11 21:09:45 +08:00

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package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.go]
const (
// RISCV32 CPU
CPU_RISCV32_ANY = 0
CPU_RISCV32_BASE32 = 1
CPU_RISCV32_SIFIVE_E31 = 2
CPU_RISCV32_SIFIVE_U34 = 3
CPU_RISCV32_ENDING = 4
// RISCV64 CPU
CPU_RISCV64_ANY = 0
CPU_RISCV64_BASE64 = 1
CPU_RISCV64_SIFIVE_E51 = 2
CPU_RISCV64_SIFIVE_U54 = 3
CPU_RISCV64_ENDING = 4
// RISCV registers
RISCV_REG_INVALID = 0
// General purpose registers
RISCV_REG_X0 = 1
RISCV_REG_X1 = 2
RISCV_REG_X2 = 3
RISCV_REG_X3 = 4
RISCV_REG_X4 = 5
RISCV_REG_X5 = 6
RISCV_REG_X6 = 7
RISCV_REG_X7 = 8
RISCV_REG_X8 = 9
RISCV_REG_X9 = 10
RISCV_REG_X10 = 11
RISCV_REG_X11 = 12
RISCV_REG_X12 = 13
RISCV_REG_X13 = 14
RISCV_REG_X14 = 15
RISCV_REG_X15 = 16
RISCV_REG_X16 = 17
RISCV_REG_X17 = 18
RISCV_REG_X18 = 19
RISCV_REG_X19 = 20
RISCV_REG_X20 = 21
RISCV_REG_X21 = 22
RISCV_REG_X22 = 23
RISCV_REG_X23 = 24
RISCV_REG_X24 = 25
RISCV_REG_X25 = 26
RISCV_REG_X26 = 27
RISCV_REG_X27 = 28
RISCV_REG_X28 = 29
RISCV_REG_X29 = 30
RISCV_REG_X30 = 31
RISCV_REG_X31 = 32
// RISCV CSR
RISCV_REG_USTATUS = 33
RISCV_REG_UIE = 34
RISCV_REG_UTVEC = 35
RISCV_REG_USCRATCH = 36
RISCV_REG_UEPC = 37
RISCV_REG_UCAUSE = 38
RISCV_REG_UTVAL = 39
RISCV_REG_UIP = 40
RISCV_REG_FFLAGS = 41
RISCV_REG_FRM = 42
RISCV_REG_FCSR = 43
RISCV_REG_CYCLE = 44
RISCV_REG_TIME = 45
RISCV_REG_INSTRET = 46
RISCV_REG_HPMCOUNTER3 = 47
RISCV_REG_HPMCOUNTER4 = 48
RISCV_REG_HPMCOUNTER5 = 49
RISCV_REG_HPMCOUNTER6 = 50
RISCV_REG_HPMCOUNTER7 = 51
RISCV_REG_HPMCOUNTER8 = 52
RISCV_REG_HPMCOUNTER9 = 53
RISCV_REG_HPMCOUNTER10 = 54
RISCV_REG_HPMCOUNTER11 = 55
RISCV_REG_HPMCOUNTER12 = 56
RISCV_REG_HPMCOUNTER13 = 57
RISCV_REG_HPMCOUNTER14 = 58
RISCV_REG_HPMCOUNTER15 = 59
RISCV_REG_HPMCOUNTER16 = 60
RISCV_REG_HPMCOUNTER17 = 61
RISCV_REG_HPMCOUNTER18 = 62
RISCV_REG_HPMCOUNTER19 = 63
RISCV_REG_HPMCOUNTER20 = 64
RISCV_REG_HPMCOUNTER21 = 65
RISCV_REG_HPMCOUNTER22 = 66
RISCV_REG_HPMCOUNTER23 = 67
RISCV_REG_HPMCOUNTER24 = 68
RISCV_REG_HPMCOUNTER25 = 69
RISCV_REG_HPMCOUNTER26 = 70
RISCV_REG_HPMCOUNTER27 = 71
RISCV_REG_HPMCOUNTER28 = 72
RISCV_REG_HPMCOUNTER29 = 73
RISCV_REG_HPMCOUNTER30 = 74
RISCV_REG_HPMCOUNTER31 = 75
RISCV_REG_CYCLEH = 76
RISCV_REG_TIMEH = 77
RISCV_REG_INSTRETH = 78
RISCV_REG_HPMCOUNTER3H = 79
RISCV_REG_HPMCOUNTER4H = 80
RISCV_REG_HPMCOUNTER5H = 81
RISCV_REG_HPMCOUNTER6H = 82
RISCV_REG_HPMCOUNTER7H = 83
RISCV_REG_HPMCOUNTER8H = 84
RISCV_REG_HPMCOUNTER9H = 85
RISCV_REG_HPMCOUNTER10H = 86
RISCV_REG_HPMCOUNTER11H = 87
RISCV_REG_HPMCOUNTER12H = 88
RISCV_REG_HPMCOUNTER13H = 89
RISCV_REG_HPMCOUNTER14H = 90
RISCV_REG_HPMCOUNTER15H = 91
RISCV_REG_HPMCOUNTER16H = 92
RISCV_REG_HPMCOUNTER17H = 93
RISCV_REG_HPMCOUNTER18H = 94
RISCV_REG_HPMCOUNTER19H = 95
RISCV_REG_HPMCOUNTER20H = 96
RISCV_REG_HPMCOUNTER21H = 97
RISCV_REG_HPMCOUNTER22H = 98
RISCV_REG_HPMCOUNTER23H = 99
RISCV_REG_HPMCOUNTER24H = 100
RISCV_REG_HPMCOUNTER25H = 101
RISCV_REG_HPMCOUNTER26H = 102
RISCV_REG_HPMCOUNTER27H = 103
RISCV_REG_HPMCOUNTER28H = 104
RISCV_REG_HPMCOUNTER29H = 105
RISCV_REG_HPMCOUNTER30H = 106
RISCV_REG_HPMCOUNTER31H = 107
RISCV_REG_MCYCLE = 108
RISCV_REG_MINSTRET = 109
RISCV_REG_MCYCLEH = 110
RISCV_REG_MINSTRETH = 111
RISCV_REG_MVENDORID = 112
RISCV_REG_MARCHID = 113
RISCV_REG_MIMPID = 114
RISCV_REG_MHARTID = 115
RISCV_REG_MSTATUS = 116
RISCV_REG_MISA = 117
RISCV_REG_MEDELEG = 118
RISCV_REG_MIDELEG = 119
RISCV_REG_MIE = 120
RISCV_REG_MTVEC = 121
RISCV_REG_MCOUNTEREN = 122
RISCV_REG_MSTATUSH = 123
RISCV_REG_MUCOUNTEREN = 124
RISCV_REG_MSCOUNTEREN = 125
RISCV_REG_MHCOUNTEREN = 126
RISCV_REG_MSCRATCH = 127
RISCV_REG_MEPC = 128
RISCV_REG_MCAUSE = 129
RISCV_REG_MTVAL = 130
RISCV_REG_MIP = 131
RISCV_REG_MBADADDR = 132
RISCV_REG_SSTATUS = 133
RISCV_REG_SEDELEG = 134
RISCV_REG_SIDELEG = 135
RISCV_REG_SIE = 136
RISCV_REG_STVEC = 137
RISCV_REG_SCOUNTEREN = 138
RISCV_REG_SSCRATCH = 139
RISCV_REG_SEPC = 140
RISCV_REG_SCAUSE = 141
RISCV_REG_STVAL = 142
RISCV_REG_SIP = 143
RISCV_REG_SBADADDR = 144
RISCV_REG_SPTBR = 145
RISCV_REG_SATP = 146
RISCV_REG_HSTATUS = 147
RISCV_REG_HEDELEG = 148
RISCV_REG_HIDELEG = 149
RISCV_REG_HIE = 150
RISCV_REG_HCOUNTEREN = 151
RISCV_REG_HTVAL = 152
RISCV_REG_HIP = 153
RISCV_REG_HTINST = 154
RISCV_REG_HGATP = 155
RISCV_REG_HTIMEDELTA = 156
RISCV_REG_HTIMEDELTAH = 157
// Floating-point registers
RISCV_REG_F0 = 158
RISCV_REG_F1 = 159
RISCV_REG_F2 = 160
RISCV_REG_F3 = 161
RISCV_REG_F4 = 162
RISCV_REG_F5 = 163
RISCV_REG_F6 = 164
RISCV_REG_F7 = 165
RISCV_REG_F8 = 166
RISCV_REG_F9 = 167
RISCV_REG_F10 = 168
RISCV_REG_F11 = 169
RISCV_REG_F12 = 170
RISCV_REG_F13 = 171
RISCV_REG_F14 = 172
RISCV_REG_F15 = 173
RISCV_REG_F16 = 174
RISCV_REG_F17 = 175
RISCV_REG_F18 = 176
RISCV_REG_F19 = 177
RISCV_REG_F20 = 178
RISCV_REG_F21 = 179
RISCV_REG_F22 = 180
RISCV_REG_F23 = 181
RISCV_REG_F24 = 182
RISCV_REG_F25 = 183
RISCV_REG_F26 = 184
RISCV_REG_F27 = 185
RISCV_REG_F28 = 186
RISCV_REG_F29 = 187
RISCV_REG_F30 = 188
RISCV_REG_F31 = 189
RISCV_REG_PC = 190
RISCV_REG_PRIV = 191
RISCV_REG_ENDING = 192
// Alias registers
RISCV_REG_ZERO = 1
RISCV_REG_RA = 2
RISCV_REG_SP = 3
RISCV_REG_GP = 4
RISCV_REG_TP = 5
RISCV_REG_T0 = 6
RISCV_REG_T1 = 7
RISCV_REG_T2 = 8
RISCV_REG_S0 = 9
RISCV_REG_FP = 9
RISCV_REG_S1 = 10
RISCV_REG_A0 = 11
RISCV_REG_A1 = 12
RISCV_REG_A2 = 13
RISCV_REG_A3 = 14
RISCV_REG_A4 = 15
RISCV_REG_A5 = 16
RISCV_REG_A6 = 17
RISCV_REG_A7 = 18
RISCV_REG_S2 = 19
RISCV_REG_S3 = 20
RISCV_REG_S4 = 21
RISCV_REG_S5 = 22
RISCV_REG_S6 = 23
RISCV_REG_S7 = 24
RISCV_REG_S8 = 25
RISCV_REG_S9 = 26
RISCV_REG_S10 = 27
RISCV_REG_S11 = 28
RISCV_REG_T3 = 29
RISCV_REG_T4 = 30
RISCV_REG_T5 = 31
RISCV_REG_T6 = 32
RISCV_REG_FT0 = 158
RISCV_REG_FT1 = 159
RISCV_REG_FT2 = 160
RISCV_REG_FT3 = 161
RISCV_REG_FT4 = 162
RISCV_REG_FT5 = 163
RISCV_REG_FT6 = 164
RISCV_REG_FT7 = 165
RISCV_REG_FS0 = 166
RISCV_REG_FS1 = 167
RISCV_REG_FA0 = 168
RISCV_REG_FA1 = 169
RISCV_REG_FA2 = 170
RISCV_REG_FA3 = 171
RISCV_REG_FA4 = 172
RISCV_REG_FA5 = 173
RISCV_REG_FA6 = 174
RISCV_REG_FA7 = 175
RISCV_REG_FS2 = 176
RISCV_REG_FS3 = 177
RISCV_REG_FS4 = 178
RISCV_REG_FS5 = 179
RISCV_REG_FS6 = 180
RISCV_REG_FS7 = 181
RISCV_REG_FS8 = 182
RISCV_REG_FS9 = 183
RISCV_REG_FS10 = 184
RISCV_REG_FS11 = 185
RISCV_REG_FT8 = 186
RISCV_REG_FT9 = 187
RISCV_REG_FT10 = 188
RISCV_REG_FT11 = 189
)
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