7d8fe2ab11
Unlike some other architectures, RISC-V does not expose the current privilege mode in any architecturally-defined register. That is intentional to make it easier to implement virtualization in software, but a Unicorn caller operates outside of the emulated hart and so it can and should be able to observe and change the current privilege mode in order to properly emulate certain behaviors of a real CPU. The current privilege level is therefore now exposed as a new pseudo-register using the name "priv", which matches the name of the virtual register used by RISC-V's debug extension to allow the debugger to read and change the privilege mode while the hart is halted. Unicorn's use of it is conceptually similar to a debugger. The bit encoding of this register is the same as specified in RISC-V Debug Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual" register exposing a subset of fields from the dcsr register, although here it's implemented directly inside the Unicorn code because QEMU doesn't currently have explicit support for the CSRs from the debug specification. If it supports "dcsr" in a future release then this implementation could change to wrap reading and writing that CSR and then projecting the "prv" and "v" bitfields into the correct locations for the virtual register.
295 lines
9.0 KiB
Forth
295 lines
9.0 KiB
Forth
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
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namespace UnicornEngine.Const
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open System
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[<AutoOpen>]
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module Riscv =
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// RISCV32 CPU
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let UC_CPU_RISCV32_ANY = 0
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let UC_CPU_RISCV32_BASE32 = 1
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let UC_CPU_RISCV32_SIFIVE_E31 = 2
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let UC_CPU_RISCV32_SIFIVE_U34 = 3
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let UC_CPU_RISCV32_ENDING = 4
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// RISCV64 CPU
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let UC_CPU_RISCV64_ANY = 0
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let UC_CPU_RISCV64_BASE64 = 1
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let UC_CPU_RISCV64_SIFIVE_E51 = 2
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let UC_CPU_RISCV64_SIFIVE_U54 = 3
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let UC_CPU_RISCV64_ENDING = 4
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// RISCV registers
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let UC_RISCV_REG_INVALID = 0
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// General purpose registers
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let UC_RISCV_REG_X0 = 1
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let UC_RISCV_REG_X1 = 2
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let UC_RISCV_REG_X2 = 3
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let UC_RISCV_REG_X3 = 4
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let UC_RISCV_REG_X4 = 5
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let UC_RISCV_REG_X5 = 6
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let UC_RISCV_REG_X6 = 7
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let UC_RISCV_REG_X7 = 8
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let UC_RISCV_REG_X8 = 9
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let UC_RISCV_REG_X9 = 10
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let UC_RISCV_REG_X10 = 11
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let UC_RISCV_REG_X11 = 12
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let UC_RISCV_REG_X12 = 13
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let UC_RISCV_REG_X13 = 14
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let UC_RISCV_REG_X14 = 15
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let UC_RISCV_REG_X15 = 16
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let UC_RISCV_REG_X16 = 17
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let UC_RISCV_REG_X17 = 18
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let UC_RISCV_REG_X18 = 19
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let UC_RISCV_REG_X19 = 20
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let UC_RISCV_REG_X20 = 21
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let UC_RISCV_REG_X21 = 22
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let UC_RISCV_REG_X22 = 23
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let UC_RISCV_REG_X23 = 24
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let UC_RISCV_REG_X24 = 25
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let UC_RISCV_REG_X25 = 26
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let UC_RISCV_REG_X26 = 27
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let UC_RISCV_REG_X27 = 28
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let UC_RISCV_REG_X28 = 29
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let UC_RISCV_REG_X29 = 30
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let UC_RISCV_REG_X30 = 31
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let UC_RISCV_REG_X31 = 32
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// RISCV CSR
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let UC_RISCV_REG_USTATUS = 33
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let UC_RISCV_REG_UIE = 34
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let UC_RISCV_REG_UTVEC = 35
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let UC_RISCV_REG_USCRATCH = 36
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let UC_RISCV_REG_UEPC = 37
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let UC_RISCV_REG_UCAUSE = 38
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let UC_RISCV_REG_UTVAL = 39
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let UC_RISCV_REG_UIP = 40
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let UC_RISCV_REG_FFLAGS = 41
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let UC_RISCV_REG_FRM = 42
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let UC_RISCV_REG_FCSR = 43
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let UC_RISCV_REG_CYCLE = 44
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let UC_RISCV_REG_TIME = 45
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let UC_RISCV_REG_INSTRET = 46
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let UC_RISCV_REG_HPMCOUNTER3 = 47
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let UC_RISCV_REG_HPMCOUNTER4 = 48
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let UC_RISCV_REG_HPMCOUNTER5 = 49
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let UC_RISCV_REG_HPMCOUNTER6 = 50
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let UC_RISCV_REG_HPMCOUNTER7 = 51
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let UC_RISCV_REG_HPMCOUNTER8 = 52
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let UC_RISCV_REG_HPMCOUNTER9 = 53
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let UC_RISCV_REG_HPMCOUNTER10 = 54
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let UC_RISCV_REG_HPMCOUNTER11 = 55
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let UC_RISCV_REG_HPMCOUNTER12 = 56
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let UC_RISCV_REG_HPMCOUNTER13 = 57
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let UC_RISCV_REG_HPMCOUNTER14 = 58
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let UC_RISCV_REG_HPMCOUNTER15 = 59
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let UC_RISCV_REG_HPMCOUNTER16 = 60
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let UC_RISCV_REG_HPMCOUNTER17 = 61
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let UC_RISCV_REG_HPMCOUNTER18 = 62
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let UC_RISCV_REG_HPMCOUNTER19 = 63
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let UC_RISCV_REG_HPMCOUNTER20 = 64
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let UC_RISCV_REG_HPMCOUNTER21 = 65
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let UC_RISCV_REG_HPMCOUNTER22 = 66
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let UC_RISCV_REG_HPMCOUNTER23 = 67
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let UC_RISCV_REG_HPMCOUNTER24 = 68
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let UC_RISCV_REG_HPMCOUNTER25 = 69
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let UC_RISCV_REG_HPMCOUNTER26 = 70
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let UC_RISCV_REG_HPMCOUNTER27 = 71
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let UC_RISCV_REG_HPMCOUNTER28 = 72
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let UC_RISCV_REG_HPMCOUNTER29 = 73
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let UC_RISCV_REG_HPMCOUNTER30 = 74
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let UC_RISCV_REG_HPMCOUNTER31 = 75
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let UC_RISCV_REG_CYCLEH = 76
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let UC_RISCV_REG_TIMEH = 77
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let UC_RISCV_REG_INSTRETH = 78
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let UC_RISCV_REG_HPMCOUNTER3H = 79
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let UC_RISCV_REG_HPMCOUNTER4H = 80
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let UC_RISCV_REG_HPMCOUNTER5H = 81
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let UC_RISCV_REG_HPMCOUNTER6H = 82
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let UC_RISCV_REG_HPMCOUNTER7H = 83
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let UC_RISCV_REG_HPMCOUNTER8H = 84
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let UC_RISCV_REG_HPMCOUNTER9H = 85
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let UC_RISCV_REG_HPMCOUNTER10H = 86
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let UC_RISCV_REG_HPMCOUNTER11H = 87
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let UC_RISCV_REG_HPMCOUNTER12H = 88
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let UC_RISCV_REG_HPMCOUNTER13H = 89
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let UC_RISCV_REG_HPMCOUNTER14H = 90
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let UC_RISCV_REG_HPMCOUNTER15H = 91
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let UC_RISCV_REG_HPMCOUNTER16H = 92
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let UC_RISCV_REG_HPMCOUNTER17H = 93
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let UC_RISCV_REG_HPMCOUNTER18H = 94
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let UC_RISCV_REG_HPMCOUNTER19H = 95
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let UC_RISCV_REG_HPMCOUNTER20H = 96
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let UC_RISCV_REG_HPMCOUNTER21H = 97
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let UC_RISCV_REG_HPMCOUNTER22H = 98
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let UC_RISCV_REG_HPMCOUNTER23H = 99
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let UC_RISCV_REG_HPMCOUNTER24H = 100
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let UC_RISCV_REG_HPMCOUNTER25H = 101
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let UC_RISCV_REG_HPMCOUNTER26H = 102
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let UC_RISCV_REG_HPMCOUNTER27H = 103
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let UC_RISCV_REG_HPMCOUNTER28H = 104
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let UC_RISCV_REG_HPMCOUNTER29H = 105
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let UC_RISCV_REG_HPMCOUNTER30H = 106
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let UC_RISCV_REG_HPMCOUNTER31H = 107
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let UC_RISCV_REG_MCYCLE = 108
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let UC_RISCV_REG_MINSTRET = 109
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let UC_RISCV_REG_MCYCLEH = 110
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let UC_RISCV_REG_MINSTRETH = 111
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let UC_RISCV_REG_MVENDORID = 112
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let UC_RISCV_REG_MARCHID = 113
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let UC_RISCV_REG_MIMPID = 114
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let UC_RISCV_REG_MHARTID = 115
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let UC_RISCV_REG_MSTATUS = 116
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let UC_RISCV_REG_MISA = 117
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let UC_RISCV_REG_MEDELEG = 118
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let UC_RISCV_REG_MIDELEG = 119
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let UC_RISCV_REG_MIE = 120
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let UC_RISCV_REG_MTVEC = 121
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let UC_RISCV_REG_MCOUNTEREN = 122
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let UC_RISCV_REG_MSTATUSH = 123
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let UC_RISCV_REG_MUCOUNTEREN = 124
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let UC_RISCV_REG_MSCOUNTEREN = 125
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let UC_RISCV_REG_MHCOUNTEREN = 126
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let UC_RISCV_REG_MSCRATCH = 127
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let UC_RISCV_REG_MEPC = 128
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let UC_RISCV_REG_MCAUSE = 129
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let UC_RISCV_REG_MTVAL = 130
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let UC_RISCV_REG_MIP = 131
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let UC_RISCV_REG_MBADADDR = 132
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let UC_RISCV_REG_SSTATUS = 133
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let UC_RISCV_REG_SEDELEG = 134
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let UC_RISCV_REG_SIDELEG = 135
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let UC_RISCV_REG_SIE = 136
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let UC_RISCV_REG_STVEC = 137
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let UC_RISCV_REG_SCOUNTEREN = 138
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let UC_RISCV_REG_SSCRATCH = 139
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let UC_RISCV_REG_SEPC = 140
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let UC_RISCV_REG_SCAUSE = 141
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let UC_RISCV_REG_STVAL = 142
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let UC_RISCV_REG_SIP = 143
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let UC_RISCV_REG_SBADADDR = 144
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let UC_RISCV_REG_SPTBR = 145
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let UC_RISCV_REG_SATP = 146
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let UC_RISCV_REG_HSTATUS = 147
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let UC_RISCV_REG_HEDELEG = 148
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let UC_RISCV_REG_HIDELEG = 149
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let UC_RISCV_REG_HIE = 150
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let UC_RISCV_REG_HCOUNTEREN = 151
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let UC_RISCV_REG_HTVAL = 152
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let UC_RISCV_REG_HIP = 153
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let UC_RISCV_REG_HTINST = 154
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let UC_RISCV_REG_HGATP = 155
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let UC_RISCV_REG_HTIMEDELTA = 156
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let UC_RISCV_REG_HTIMEDELTAH = 157
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// Floating-point registers
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let UC_RISCV_REG_F0 = 158
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let UC_RISCV_REG_F1 = 159
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let UC_RISCV_REG_F2 = 160
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let UC_RISCV_REG_F3 = 161
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let UC_RISCV_REG_F4 = 162
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let UC_RISCV_REG_F5 = 163
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let UC_RISCV_REG_F6 = 164
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let UC_RISCV_REG_F7 = 165
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let UC_RISCV_REG_F8 = 166
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let UC_RISCV_REG_F9 = 167
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let UC_RISCV_REG_F10 = 168
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let UC_RISCV_REG_F11 = 169
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let UC_RISCV_REG_F12 = 170
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let UC_RISCV_REG_F13 = 171
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let UC_RISCV_REG_F14 = 172
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let UC_RISCV_REG_F15 = 173
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let UC_RISCV_REG_F16 = 174
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let UC_RISCV_REG_F17 = 175
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let UC_RISCV_REG_F18 = 176
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let UC_RISCV_REG_F19 = 177
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let UC_RISCV_REG_F20 = 178
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let UC_RISCV_REG_F21 = 179
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let UC_RISCV_REG_F22 = 180
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let UC_RISCV_REG_F23 = 181
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let UC_RISCV_REG_F24 = 182
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let UC_RISCV_REG_F25 = 183
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let UC_RISCV_REG_F26 = 184
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let UC_RISCV_REG_F27 = 185
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let UC_RISCV_REG_F28 = 186
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let UC_RISCV_REG_F29 = 187
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let UC_RISCV_REG_F30 = 188
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let UC_RISCV_REG_F31 = 189
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let UC_RISCV_REG_PC = 190
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let UC_RISCV_REG_PRIV = 191
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let UC_RISCV_REG_ENDING = 192
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// Alias registers
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let UC_RISCV_REG_ZERO = 1
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let UC_RISCV_REG_RA = 2
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let UC_RISCV_REG_SP = 3
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let UC_RISCV_REG_GP = 4
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let UC_RISCV_REG_TP = 5
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let UC_RISCV_REG_T0 = 6
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let UC_RISCV_REG_T1 = 7
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let UC_RISCV_REG_T2 = 8
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let UC_RISCV_REG_S0 = 9
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let UC_RISCV_REG_FP = 9
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let UC_RISCV_REG_S1 = 10
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let UC_RISCV_REG_A0 = 11
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let UC_RISCV_REG_A1 = 12
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let UC_RISCV_REG_A2 = 13
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let UC_RISCV_REG_A3 = 14
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let UC_RISCV_REG_A4 = 15
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let UC_RISCV_REG_A5 = 16
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let UC_RISCV_REG_A6 = 17
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let UC_RISCV_REG_A7 = 18
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let UC_RISCV_REG_S2 = 19
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let UC_RISCV_REG_S3 = 20
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let UC_RISCV_REG_S4 = 21
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let UC_RISCV_REG_S5 = 22
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let UC_RISCV_REG_S6 = 23
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let UC_RISCV_REG_S7 = 24
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let UC_RISCV_REG_S8 = 25
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let UC_RISCV_REG_S9 = 26
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let UC_RISCV_REG_S10 = 27
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let UC_RISCV_REG_S11 = 28
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let UC_RISCV_REG_T3 = 29
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let UC_RISCV_REG_T4 = 30
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let UC_RISCV_REG_T5 = 31
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let UC_RISCV_REG_T6 = 32
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let UC_RISCV_REG_FT0 = 158
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let UC_RISCV_REG_FT1 = 159
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let UC_RISCV_REG_FT2 = 160
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let UC_RISCV_REG_FT3 = 161
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let UC_RISCV_REG_FT4 = 162
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let UC_RISCV_REG_FT5 = 163
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let UC_RISCV_REG_FT6 = 164
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let UC_RISCV_REG_FT7 = 165
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let UC_RISCV_REG_FS0 = 166
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let UC_RISCV_REG_FS1 = 167
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let UC_RISCV_REG_FA0 = 168
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let UC_RISCV_REG_FA1 = 169
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let UC_RISCV_REG_FA2 = 170
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let UC_RISCV_REG_FA3 = 171
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let UC_RISCV_REG_FA4 = 172
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let UC_RISCV_REG_FA5 = 173
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let UC_RISCV_REG_FA6 = 174
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let UC_RISCV_REG_FA7 = 175
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let UC_RISCV_REG_FS2 = 176
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let UC_RISCV_REG_FS3 = 177
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let UC_RISCV_REG_FS4 = 178
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let UC_RISCV_REG_FS5 = 179
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let UC_RISCV_REG_FS6 = 180
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let UC_RISCV_REG_FS7 = 181
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let UC_RISCV_REG_FS8 = 182
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let UC_RISCV_REG_FS9 = 183
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let UC_RISCV_REG_FS10 = 184
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let UC_RISCV_REG_FS11 = 185
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let UC_RISCV_REG_FT8 = 186
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let UC_RISCV_REG_FT9 = 187
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let UC_RISCV_REG_FT10 = 188
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let UC_RISCV_REG_FT11 = 189
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