469 lines
14 KiB
C
469 lines
14 KiB
C
/*
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* s390x SIGP instruction handling
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*
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* Copyright (c) 2009 Alexander Graf <agraf@suse.de>
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* Copyright IBM Corp. 2012
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internal.h"
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//#include "exec/address-spaces.h"
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#include "exec/exec-all.h"
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#include "sysemu/tcg.h"
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typedef struct SigpInfo {
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uint64_t param;
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int cc;
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uint64_t *status_reg;
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} SigpInfo;
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// static void set_sigp_status(SigpInfo *si, uint64_t status)
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// {
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// *si->status_reg &= 0xffffffff00000000ULL;
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// *si->status_reg |= status;
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// si->cc = SIGP_CC_STATUS_STORED;
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// }
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// static void sigp_sense(S390CPU *dst_cpu, SigpInfo *si)
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// {
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// uint8_t state = s390_cpu_get_state(dst_cpu);
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// bool ext_call = dst_cpu->env.pending_int & INTERRUPT_EXTERNAL_CALL;
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// uint64_t status = 0;
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// /* sensing without locks is racy, but it's the same for real hw */
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// if (state != S390_CPU_STATE_STOPPED && !ext_call) {
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// si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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// } else {
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// if (ext_call) {
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// status |= SIGP_STAT_EXT_CALL_PENDING;
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// }
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// if (state == S390_CPU_STATE_STOPPED) {
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// status |= SIGP_STAT_STOPPED;
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// }
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// set_sigp_status(si, status);
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// }
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// }
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// static void sigp_external_call(S390CPU *src_cpu, S390CPU *dst_cpu, SigpInfo *si)
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// {
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// int ret;
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// ret = cpu_inject_external_call(dst_cpu, src_cpu->env.core_id);
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// if (!ret) {
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// si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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// } else {
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// set_sigp_status(si, SIGP_STAT_EXT_CALL_PENDING);
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// }
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// }
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// static void sigp_emergency(S390CPU *src_cpu, S390CPU *dst_cpu, SigpInfo *si)
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// {
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// cpu_inject_emergency_signal(dst_cpu, src_cpu->env.core_id);
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// si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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// }
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#if 0
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static void sigp_start(CPUState *cs, run_on_cpu_data arg)
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{
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S390CPU *cpu = S390_CPU(cs);
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SigpInfo *si = arg.host_ptr;
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if (s390_cpu_get_state(cpu) != S390_CPU_STATE_STOPPED) {
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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return;
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}
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s390_cpu_set_state(S390_CPU_STATE_OPERATING, cpu);
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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static void sigp_stop(CPUState *cs, run_on_cpu_data arg)
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{
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S390CPU *cpu = S390_CPU(cs);
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SigpInfo *si = arg.host_ptr;
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if (s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING) {
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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return;
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}
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/* disabled wait - sleeping in user space */
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if (cs->halted) {
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s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
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} else {
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/* execute the stop function */
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cpu->env.sigp_order = SIGP_STOP;
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cpu_inject_stop(cpu);
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}
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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static void sigp_stop_and_store_status(CPUState *cs, run_on_cpu_data arg)
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{
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S390CPU *cpu = S390_CPU(cs);
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SigpInfo *si = arg.host_ptr;
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/* disabled wait - sleeping in user space */
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if (s390_cpu_get_state(cpu) == S390_CPU_STATE_OPERATING && cs->halted) {
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s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
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}
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switch (s390_cpu_get_state(cpu)) {
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case S390_CPU_STATE_OPERATING:
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cpu->env.sigp_order = SIGP_STOP_STORE_STATUS;
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cpu_inject_stop(cpu);
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/* store will be performed in do_stop_interrup() */
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break;
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case S390_CPU_STATE_STOPPED:
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/* already stopped, just store the status */
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// cpu_synchronize_state(cs);
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s390_store_status(cpu, S390_STORE_STATUS_DEF_ADDR, true);
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break;
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}
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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static void sigp_store_status_at_address(CPUState *cs, run_on_cpu_data arg)
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{
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S390CPU *cpu = S390_CPU(cs);
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SigpInfo *si = arg.host_ptr;
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uint32_t address = si->param & 0x7ffffe00u;
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/* cpu has to be stopped */
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if (s390_cpu_get_state(cpu) != S390_CPU_STATE_STOPPED) {
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set_sigp_status(si, SIGP_STAT_INCORRECT_STATE);
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return;
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}
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// cpu_synchronize_state(cs);
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if (s390_store_status(cpu, address, false)) {
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set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
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return;
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}
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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#define ADTL_SAVE_LC_MASK 0xfUL
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static void sigp_store_adtl_status(CPUState *cs, run_on_cpu_data arg)
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{
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S390CPU *cpu = S390_CPU(cs);
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SigpInfo *si = arg.host_ptr;
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uint8_t lc = si->param & ADTL_SAVE_LC_MASK;
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hwaddr addr = si->param & ~ADTL_SAVE_LC_MASK;
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hwaddr len = 1UL << (lc ? lc : 10);
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if (!s390_has_feat(S390_FEAT_VECTOR) &&
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!s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
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set_sigp_status(si, SIGP_STAT_INVALID_ORDER);
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return;
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}
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/* cpu has to be stopped */
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if (s390_cpu_get_state(cpu) != S390_CPU_STATE_STOPPED) {
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set_sigp_status(si, SIGP_STAT_INCORRECT_STATE);
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return;
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}
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/* address must be aligned to length */
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if (addr & (len - 1)) {
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set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
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return;
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}
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/* no GS: only lc == 0 is valid */
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if (!s390_has_feat(S390_FEAT_GUARDED_STORAGE) &&
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lc != 0) {
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set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
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return;
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}
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/* GS: 0, 10, 11, 12 are valid */
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if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) &&
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lc != 0 &&
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lc != 10 &&
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lc != 11 &&
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lc != 12) {
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set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
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return;
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}
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// cpu_synchronize_state(cs);
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if (s390_store_adtl_status(cpu, addr, len)) {
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set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
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return;
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}
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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static void sigp_restart(CPUState *cs, run_on_cpu_data arg)
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{
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S390CPU *cpu = S390_CPU(cs);
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SigpInfo *si = arg.host_ptr;
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switch (s390_cpu_get_state(cpu)) {
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case S390_CPU_STATE_STOPPED:
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/* the restart irq has to be delivered prior to any other pending irq */
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// cpu_synchronize_state(cs);
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/*
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* Set OPERATING (and unhalting) before loading the restart PSW.
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* load_psw() will then properly halt the CPU again if necessary (TCG).
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*/
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s390_cpu_set_state(S390_CPU_STATE_OPERATING, cpu);
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do_restart_interrupt(&cpu->env);
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break;
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case S390_CPU_STATE_OPERATING:
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cpu_inject_restart(cpu);
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break;
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}
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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static void sigp_initial_cpu_reset(CPUState *cs, run_on_cpu_data arg)
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{
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S390CPU *cpu = S390_CPU(cs);
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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SigpInfo *si = arg.host_ptr;
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// cpu_synchronize_state(cs);
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scc->reset(cs, S390_CPU_RESET_INITIAL);
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// cpu_synchronize_post_reset(cs);
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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static void sigp_cpu_reset(CPUState *cs, run_on_cpu_data arg)
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{
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S390CPU *cpu = S390_CPU(cs);
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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SigpInfo *si = arg.host_ptr;
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// cpu_synchronize_state(cs);
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scc->reset(cs, S390_CPU_RESET_NORMAL);
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// cpu_synchronize_post_reset(cs);
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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SigpInfo *si = arg.host_ptr;
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uint32_t addr = si->param & 0x7fffe000u;
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// cpu_synchronize_state(cs);
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if (!address_space_access_valid(env_cpu(env)->as, addr,
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sizeof(struct LowCore), false,
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MEMTXATTRS_UNSPECIFIED)) {
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set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
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return;
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}
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/* cpu has to be stopped */
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if (s390_cpu_get_state(cpu) != S390_CPU_STATE_STOPPED) {
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set_sigp_status(si, SIGP_STAT_INCORRECT_STATE);
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return;
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}
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cpu->env.psa = addr;
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tlb_flush(cs);
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// cpu_synchronize_post_init(cs);
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si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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}
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#endif
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// static void sigp_cond_emergency(S390CPU *src_cpu, S390CPU *dst_cpu,
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// SigpInfo *si)
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// {
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// const uint64_t psw_int_mask = PSW_MASK_IO | PSW_MASK_EXT;
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// uint16_t p_asn, s_asn, asn;
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// uint64_t psw_addr, psw_mask;
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// bool idle;
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// /* this looks racy, but these values are only used when STOPPED */
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// idle = CPU(dst_cpu)->halted;
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// psw_addr = dst_cpu->env.psw.addr;
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// psw_mask = dst_cpu->env.psw.mask;
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// asn = si->param;
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// p_asn = dst_cpu->env.cregs[4] & 0xffff; /* Primary ASN */
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// s_asn = dst_cpu->env.cregs[3] & 0xffff; /* Secondary ASN */
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// if (s390_cpu_get_state(dst_cpu) != S390_CPU_STATE_STOPPED ||
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// (psw_mask & psw_int_mask) != psw_int_mask ||
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// (idle && psw_addr != 0) ||
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// (!idle && (asn == p_asn || asn == s_asn))) {
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// cpu_inject_emergency_signal(dst_cpu, src_cpu->env.core_id);
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// } else {
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// set_sigp_status(si, SIGP_STAT_INCORRECT_STATE);
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// }
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// si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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// }
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// static void sigp_sense_running(S390CPU *dst_cpu, SigpInfo *si)
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// {
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// /* sensing without locks is racy, but it's the same for real hw */
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// //if (!s390_has_feat(S390_FEAT_SENSE_RUNNING_STATUS)) {
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// // set_sigp_status(si, SIGP_STAT_INVALID_ORDER);
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// // return;
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// //}
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// /* If halted (which includes also STOPPED), it is not running */
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// if (CPU(dst_cpu)->halted) {
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// set_sigp_status(si, SIGP_STAT_NOT_RUNNING);
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// } else {
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// si->cc = SIGP_CC_ORDER_CODE_ACCEPTED;
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// }
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// }
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// static int handle_sigp_single_dst(S390CPU *cpu, S390CPU *dst_cpu, uint8_t order,
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// uint64_t param, uint64_t *status_reg)
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// {
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// SigpInfo si = {
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// .param = param,
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// .status_reg = status_reg,
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// };
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// /* cpu available? */
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// if (dst_cpu == NULL) {
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// return SIGP_CC_NOT_OPERATIONAL;
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// }
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// /* only resets can break pending orders */
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// if (dst_cpu->env.sigp_order != 0 &&
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// order != SIGP_CPU_RESET &&
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// order != SIGP_INITIAL_CPU_RESET) {
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// return SIGP_CC_BUSY;
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// }
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// switch (order) {
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// case SIGP_SENSE:
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// sigp_sense(dst_cpu, &si);
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// break;
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// case SIGP_EXTERNAL_CALL:
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// sigp_external_call(cpu, dst_cpu, &si);
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// break;
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// case SIGP_EMERGENCY:
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// sigp_emergency(cpu, dst_cpu, &si);
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// break;
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// case SIGP_START:
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// //run_on_cpu(CPU(dst_cpu), sigp_start, RUN_ON_CPU_HOST_PTR(&si));
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// break;
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// case SIGP_STOP:
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// //run_on_cpu(CPU(dst_cpu), sigp_stop, RUN_ON_CPU_HOST_PTR(&si));
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// break;
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// case SIGP_RESTART:
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// //run_on_cpu(CPU(dst_cpu), sigp_restart, RUN_ON_CPU_HOST_PTR(&si));
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// break;
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// case SIGP_STOP_STORE_STATUS:
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// //run_on_cpu(CPU(dst_cpu), sigp_stop_and_store_status, RUN_ON_CPU_HOST_PTR(&si));
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// break;
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// case SIGP_STORE_STATUS_ADDR:
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// //run_on_cpu(CPU(dst_cpu), sigp_store_status_at_address, RUN_ON_CPU_HOST_PTR(&si));
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// break;
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// case SIGP_STORE_ADTL_STATUS:
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// //run_on_cpu(CPU(dst_cpu), sigp_store_adtl_status, RUN_ON_CPU_HOST_PTR(&si));
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// break;
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// case SIGP_SET_PREFIX:
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// //run_on_cpu(CPU(dst_cpu), sigp_set_prefix, RUN_ON_CPU_HOST_PTR(&si));
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// break;
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// case SIGP_INITIAL_CPU_RESET:
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// //run_on_cpu(CPU(dst_cpu), sigp_initial_cpu_reset, RUN_ON_CPU_HOST_PTR(&si));
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// break;
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// case SIGP_CPU_RESET:
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// //run_on_cpu(CPU(dst_cpu), sigp_cpu_reset, RUN_ON_CPU_HOST_PTR(&si));
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// break;
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// case SIGP_COND_EMERGENCY:
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// sigp_cond_emergency(cpu, dst_cpu, &si);
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// break;
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// case SIGP_SENSE_RUNNING:
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// sigp_sense_running(dst_cpu, &si);
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// break;
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// default:
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// set_sigp_status(&si, SIGP_STAT_INVALID_ORDER);
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// }
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// return si.cc;
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// }
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// static int sigp_set_architecture(S390CPU *cpu, uint32_t param,
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// uint64_t *status_reg)
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// {
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// bool all_stopped = true;
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// #if 0
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// CPU_FOREACH(cur_cs) {
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// cur_cpu = S390_CPU(cur_cs);
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// if (cur_cpu == cpu) {
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// continue;
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// }
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// if (s390_cpu_get_state(cur_cpu) != S390_CPU_STATE_STOPPED) {
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// all_stopped = false;
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// }
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// }
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// #endif
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// all_stopped = false;
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// *status_reg &= 0xffffffff00000000ULL;
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// /* Reject set arch order, with czam we're always in z/Arch mode. */
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// *status_reg |= (all_stopped ? SIGP_STAT_INVALID_PARAMETER :
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// SIGP_STAT_INCORRECT_STATE);
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// return SIGP_CC_STATUS_STORED;
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// }
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#if 0
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int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3)
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{
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uint64_t *status_reg = &env->regs[r1];
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uint64_t param = (r1 % 2) ? env->regs[r1] : env->regs[r1 + 1];
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S390CPU *cpu = env_archcpu(env);
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S390CPU *dst_cpu = NULL;
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int ret;
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switch (order) {
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case SIGP_SET_ARCH:
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ret = sigp_set_architecture(cpu, param, status_reg);
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break;
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default:
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/* all other sigp orders target a single vcpu */
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dst_cpu = s390_cpu_addr2state(env->regs[r3]);
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ret = handle_sigp_single_dst(cpu, dst_cpu, order, param, status_reg);
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}
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return ret;
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}
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#endif
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int s390_cpu_restart(S390CPU *cpu)
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{
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//SigpInfo si = {};
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//run_on_cpu(CPU(cpu), sigp_restart, RUN_ON_CPU_HOST_PTR(&si));
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return 0;
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}
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void do_stop_interrupt(CPUS390XState *env)
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{
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S390CPU *cpu = env_archcpu(env);
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if (s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu) == 0) {
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// qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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}
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if (cpu->env.sigp_order == SIGP_STOP_STORE_STATUS) {
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s390_store_status(cpu, S390_STORE_STATUS_DEF_ADDR, true);
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}
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env->sigp_order = 0;
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env->pending_int &= ~INTERRUPT_STOP;
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}
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|
|
|
void s390_init_sigp(void)
|
|
{
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|
}
|