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074566cf697bfa38b3c9dd283c52ef4e4549c208
unicorn/qemu/target/tricore/unicorn.c
Robert Xiao 074566cf69 Slight refactoring to reduce code duplication. 
This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
2023-06-16 15:23:42 -07:00

362 lines
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/* Unicorn Emulator Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
/*
Created for Unicorn Engine by Eric Poole <eric.poole@aptiv.com>, 2022
Copyright 2022 Aptiv
*/
#include "qemu/typedefs.h"
#include "unicorn/unicorn.h"
#include "sysemu/cpus.h"
#include "sysemu/tcg.h"
#include "cpu.h"
#include "uc_priv.h"
#include "unicorn_common.h"
#include "unicorn.h"
TriCoreCPU *cpu_tricore_init(struct uc_struct *uc);
static void tricore_set_pc(struct uc_struct *uc, uint64_t address)
{
((CPUTriCoreState *)uc->cpu->env_ptr)->PC = address;
}
static uint64_t tricore_get_pc(struct uc_struct *uc)
{
return ((CPUTriCoreState *)uc->cpu->env_ptr)->PC;
}
void tricore_reg_reset(struct uc_struct *uc)
{
CPUTriCoreState *env;
(void)uc;
env = uc->cpu->env_ptr;
memset(env->gpr_a, 0, sizeof(env->gpr_a));
memset(env->gpr_d, 0, sizeof(env->gpr_d));
env->PC = 0;
}
static uc_err reg_read(CPUTriCoreState *env, unsigned int regid, void *value,
size_t *size)
{
uc_err ret = UC_ERR_ARG;
if (regid >= UC_TRICORE_REG_A0 && regid <= UC_TRICORE_REG_A9) {
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->gpr_a[regid - UC_TRICORE_REG_A0];
} else if (regid >= UC_TRICORE_REG_A12 && regid <= UC_TRICORE_REG_A15) {
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->gpr_a[regid - UC_TRICORE_REG_A0];
} else if (regid >= UC_TRICORE_REG_D0 && regid <= UC_TRICORE_REG_D15) {
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->gpr_d[regid - UC_TRICORE_REG_D0];
} else {
switch (regid) {
// case UC_TRICORE_REG_SP:
case UC_TRICORE_REG_A10:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->gpr_a[10];
break;
// case UC_TRICORE_REG_LR:
case UC_TRICORE_REG_A11:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->gpr_a[11];
break;
case UC_TRICORE_REG_PC:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->PC;
break;
case UC_TRICORE_REG_PCXI:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->PCXI;
break;
case UC_TRICORE_REG_PSW:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->PSW;
break;
case UC_TRICORE_REG_PSW_USB_C:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->PSW_USB_C;
break;
case UC_TRICORE_REG_PSW_USB_V:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->PSW_USB_V;
break;
case UC_TRICORE_REG_PSW_USB_SV:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->PSW_USB_SV;
break;
case UC_TRICORE_REG_PSW_USB_AV:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->PSW_USB_AV;
break;
case UC_TRICORE_REG_PSW_USB_SAV:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->PSW_USB_SAV;
break;
case UC_TRICORE_REG_SYSCON:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->SYSCON;
break;
case UC_TRICORE_REG_CPU_ID:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->CPU_ID;
break;
case UC_TRICORE_REG_BIV:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->BIV;
break;
case UC_TRICORE_REG_BTV:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->BTV;
break;
case UC_TRICORE_REG_ISP:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->ISP;
break;
case UC_TRICORE_REG_ICR:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->ICR;
break;
case UC_TRICORE_REG_FCX:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->FCX;
break;
case UC_TRICORE_REG_LCX:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->LCX;
break;
case UC_TRICORE_REG_COMPAT:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->COMPAT;
break;
}
}
return ret;
}
static uc_err reg_write(CPUTriCoreState *env, unsigned int regid,
const void *value, size_t *size, int *setpc)
{
uc_err ret = UC_ERR_ARG;
if (regid >= UC_TRICORE_REG_A0 && regid <= UC_TRICORE_REG_A9) {
CHECK_REG_TYPE(uint32_t);
env->gpr_a[regid - UC_TRICORE_REG_A0] = *(uint32_t *)value;
} else if (regid >= UC_TRICORE_REG_A12 && regid <= UC_TRICORE_REG_A15) {
CHECK_REG_TYPE(uint32_t);
env->gpr_a[regid - UC_TRICORE_REG_A0] = *(uint32_t *)value;
} else if (regid >= UC_TRICORE_REG_D0 && regid <= UC_TRICORE_REG_D15) {
CHECK_REG_TYPE(uint32_t);
env->gpr_d[regid - UC_TRICORE_REG_D0] = *(uint32_t *)value;
} else {
switch (regid) {
// case UC_TRICORE_REG_SP:
case UC_TRICORE_REG_A10:
CHECK_REG_TYPE(uint32_t);
env->gpr_a[10] = *(uint32_t *)value;
break;
// case UC_TRICORE_REG_LR:
case UC_TRICORE_REG_A11:
CHECK_REG_TYPE(uint32_t);
env->gpr_a[11] = *(uint32_t *)value;
break;
case UC_TRICORE_REG_PC:
CHECK_REG_TYPE(uint32_t);
env->PC = *(uint32_t *)value;
*setpc = 1;
break;
case UC_TRICORE_REG_PCXI:
CHECK_REG_TYPE(uint32_t);
env->PCXI = *(uint32_t *)value;
break;
case UC_TRICORE_REG_PSW:
CHECK_REG_TYPE(uint32_t);
env->PSW = *(uint32_t *)value;
break;
case UC_TRICORE_REG_PSW_USB_C:
CHECK_REG_TYPE(uint32_t);
env->PSW_USB_C = *(uint32_t *)value;
break;
case UC_TRICORE_REG_PSW_USB_V:
CHECK_REG_TYPE(uint32_t);
env->PSW_USB_V = *(uint32_t *)value;
break;
case UC_TRICORE_REG_PSW_USB_SV:
CHECK_REG_TYPE(uint32_t);
env->PSW_USB_SV = *(uint32_t *)value;
break;
case UC_TRICORE_REG_PSW_USB_AV:
CHECK_REG_TYPE(uint32_t);
env->PSW_USB_AV = *(uint32_t *)value;
break;
case UC_TRICORE_REG_PSW_USB_SAV:
CHECK_REG_TYPE(uint32_t);
env->PSW_USB_SAV = *(uint32_t *)value;
break;
case UC_TRICORE_REG_SYSCON:
CHECK_REG_TYPE(uint32_t);
env->SYSCON = *(uint32_t *)value;
break;
case UC_TRICORE_REG_CPU_ID:
CHECK_REG_TYPE(uint32_t);
env->CPU_ID = *(uint32_t *)value;
break;
case UC_TRICORE_REG_BIV:
CHECK_REG_TYPE(uint32_t);
env->BIV = *(uint32_t *)value;
break;
case UC_TRICORE_REG_BTV:
CHECK_REG_TYPE(uint32_t);
env->BTV = *(uint32_t *)value;
break;
case UC_TRICORE_REG_ISP:
CHECK_REG_TYPE(uint32_t);
env->ISP = *(uint32_t *)value;
break;
case UC_TRICORE_REG_ICR:
CHECK_REG_TYPE(uint32_t);
env->ICR = *(uint32_t *)value;
break;
case UC_TRICORE_REG_FCX:
CHECK_REG_TYPE(uint32_t);
env->FCX = *(uint32_t *)value;
break;
case UC_TRICORE_REG_LCX:
CHECK_REG_TYPE(uint32_t);
env->LCX = *(uint32_t *)value;
break;
case UC_TRICORE_REG_COMPAT:
CHECK_REG_TYPE(uint32_t);
env->COMPAT = *(uint32_t *)value;
break;
}
}
return ret;
}
static uc_err reg_read_batch(CPUTriCoreState *env, unsigned int *regs,
void *const *vals, size_t *sizes, int count)
{
int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
void *value = vals[i];
uc_err err = reg_read(env, regid, value, sizes ? sizes + i : NULL);
if (err) {
return err;
}
}
return UC_ERR_OK;
}
static uc_err reg_write_batch(CPUTriCoreState *env, unsigned int *regs,
const void *const *vals, size_t *sizes, int count,
int *setpc)
{
int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
const void *value = vals[i];
uc_err err =
reg_write(env, regid, value, sizes ? sizes + i : NULL, setpc);
if (err) {
return err;
}
}
return UC_ERR_OK;
}
int tricore_reg_read(struct uc_struct *uc, unsigned int *regs,
void *const *vals, size_t *sizes, int count)
{
CPUTriCoreState *env = &(TRICORE_CPU(uc->cpu)->env);
return reg_read_batch(env, regs, vals, sizes, count);
}
int tricore_reg_write(struct uc_struct *uc, unsigned int *regs,
const void *const *vals, size_t *sizes, int count)
{
CPUTriCoreState *env = &(TRICORE_CPU(uc->cpu)->env);
int setpc = 0;
uc_err err = reg_write_batch(env, regs, vals, sizes, count, &setpc);
if (err) {
return err;
}
if (setpc) {
// force to quit execution and flush TB
uc->quit_request = true;
break_translation_loop(uc);
}
return UC_ERR_OK;
}
int tricore_context_reg_read(struct uc_context *uc, unsigned int *regs,
void *const *vals, size_t *sizes, int count)
{
CPUTriCoreState *env = (CPUTriCoreState *)uc->data;
return reg_read_batch(env, regs, vals, sizes, count);
}
int tricore_context_reg_write(struct uc_context *uc, unsigned int *regs,
const void *const *vals, size_t *sizes, int count)
{
CPUTriCoreState *env = (CPUTriCoreState *)uc->data;
int setpc = 0;
return reg_write_batch(env, regs, vals, sizes, count, &setpc);
}
static int tricore_cpus_init(struct uc_struct *uc, const char *cpu_model)
{
TriCoreCPU *cpu;
cpu = cpu_tricore_init(uc);
if (cpu == NULL) {
return -1;
}
return 0;
}
static void tricore_release(void *ctx)
{
int i;
TCGContext *tcg_ctx = (TCGContext *)ctx;
TriCoreCPU *cpu = (TriCoreCPU *)tcg_ctx->uc->cpu;
CPUTLBDesc *d = cpu->neg.tlb.d;
CPUTLBDescFast *f = cpu->neg.tlb.f;
CPUTLBDesc *desc;
CPUTLBDescFast *fast;
release_common(ctx);
for (i = 0; i < NB_MMU_MODES; i++) {
desc = &(d[i]);
fast = &(f[i]);
g_free(desc->iotlb);
g_free(fast->table);
}
}
void tricore_uc_init(struct uc_struct *uc)
{
uc->reg_read = tricore_reg_read;
uc->reg_write = tricore_reg_write;
uc->reg_reset = tricore_reg_reset;
uc->set_pc = tricore_set_pc;
uc->get_pc = tricore_get_pc;
uc->cpus_init = tricore_cpus_init;
uc->release = tricore_release;
uc->cpu_context_size = offsetof(CPUTriCoreState, end_reset_fields);
uc_common_init(uc);
}
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