293 lines
8.8 KiB
C
293 lines
8.8 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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/*
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Created for Unicorn Engine by Eric Poole <eric.poole@aptiv.com>, 2022
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Copyright 2022 Aptiv
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*/
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#include "qemu/typedefs.h"
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#include "unicorn/unicorn.h"
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#include "sysemu/cpus.h"
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#include "sysemu/tcg.h"
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#include "cpu.h"
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#include "uc_priv.h"
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#include "unicorn_common.h"
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#include "unicorn.h"
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TriCoreCPU *cpu_tricore_init(struct uc_struct *uc);
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static void tricore_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUTriCoreState *)uc->cpu->env_ptr)->PC = address;
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}
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static uint64_t tricore_get_pc(struct uc_struct *uc)
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{
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return ((CPUTriCoreState *)uc->cpu->env_ptr)->PC;
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}
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static void reg_reset(struct uc_struct *uc)
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{
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CPUTriCoreState *env;
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(void)uc;
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env = uc->cpu->env_ptr;
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memset(env->gpr_a, 0, sizeof(env->gpr_a));
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memset(env->gpr_d, 0, sizeof(env->gpr_d));
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env->PC = 0;
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}
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DEFAULT_VISIBILITY
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uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
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size_t *size)
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{
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CPUTriCoreState *env = _env;
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uc_err ret = UC_ERR_ARG;
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if (regid >= UC_TRICORE_REG_A0 && regid <= UC_TRICORE_REG_A9) {
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->gpr_a[regid - UC_TRICORE_REG_A0];
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} else if (regid >= UC_TRICORE_REG_A12 && regid <= UC_TRICORE_REG_A15) {
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->gpr_a[regid - UC_TRICORE_REG_A0];
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} else if (regid >= UC_TRICORE_REG_D0 && regid <= UC_TRICORE_REG_D15) {
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->gpr_d[regid - UC_TRICORE_REG_D0];
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} else {
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switch (regid) {
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// case UC_TRICORE_REG_SP:
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case UC_TRICORE_REG_A10:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->gpr_a[10];
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break;
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// case UC_TRICORE_REG_LR:
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case UC_TRICORE_REG_A11:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->gpr_a[11];
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break;
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case UC_TRICORE_REG_PC:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->PC;
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break;
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case UC_TRICORE_REG_PCXI:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->PCXI;
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break;
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case UC_TRICORE_REG_PSW:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->PSW;
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break;
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case UC_TRICORE_REG_PSW_USB_C:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->PSW_USB_C;
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break;
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case UC_TRICORE_REG_PSW_USB_V:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->PSW_USB_V;
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break;
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case UC_TRICORE_REG_PSW_USB_SV:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->PSW_USB_SV;
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break;
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case UC_TRICORE_REG_PSW_USB_AV:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->PSW_USB_AV;
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break;
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case UC_TRICORE_REG_PSW_USB_SAV:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->PSW_USB_SAV;
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break;
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case UC_TRICORE_REG_SYSCON:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->SYSCON;
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break;
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case UC_TRICORE_REG_CPU_ID:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->CPU_ID;
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break;
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case UC_TRICORE_REG_BIV:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->BIV;
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break;
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case UC_TRICORE_REG_BTV:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->BTV;
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break;
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case UC_TRICORE_REG_ISP:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->ISP;
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break;
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case UC_TRICORE_REG_ICR:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->ICR;
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break;
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case UC_TRICORE_REG_FCX:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->FCX;
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break;
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case UC_TRICORE_REG_LCX:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->LCX;
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break;
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case UC_TRICORE_REG_COMPAT:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->COMPAT;
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break;
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}
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}
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CHECK_RET_DEPRECATE(ret, regid);
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return ret;
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}
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DEFAULT_VISIBILITY
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uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
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size_t *size, int *setpc)
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{
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CPUTriCoreState *env = _env;
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uc_err ret = UC_ERR_ARG;
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if (regid >= UC_TRICORE_REG_A0 && regid <= UC_TRICORE_REG_A9) {
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CHECK_REG_TYPE(uint32_t);
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env->gpr_a[regid - UC_TRICORE_REG_A0] = *(uint32_t *)value;
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} else if (regid >= UC_TRICORE_REG_A12 && regid <= UC_TRICORE_REG_A15) {
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CHECK_REG_TYPE(uint32_t);
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env->gpr_a[regid - UC_TRICORE_REG_A0] = *(uint32_t *)value;
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} else if (regid >= UC_TRICORE_REG_D0 && regid <= UC_TRICORE_REG_D15) {
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CHECK_REG_TYPE(uint32_t);
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env->gpr_d[regid - UC_TRICORE_REG_D0] = *(uint32_t *)value;
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} else {
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switch (regid) {
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// case UC_TRICORE_REG_SP:
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case UC_TRICORE_REG_A10:
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CHECK_REG_TYPE(uint32_t);
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env->gpr_a[10] = *(uint32_t *)value;
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break;
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// case UC_TRICORE_REG_LR:
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case UC_TRICORE_REG_A11:
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CHECK_REG_TYPE(uint32_t);
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env->gpr_a[11] = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_PC:
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CHECK_REG_TYPE(uint32_t);
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env->PC = *(uint32_t *)value;
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*setpc = 1;
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break;
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case UC_TRICORE_REG_PCXI:
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CHECK_REG_TYPE(uint32_t);
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env->PCXI = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_PSW:
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CHECK_REG_TYPE(uint32_t);
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env->PSW = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_PSW_USB_C:
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CHECK_REG_TYPE(uint32_t);
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env->PSW_USB_C = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_PSW_USB_V:
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CHECK_REG_TYPE(uint32_t);
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env->PSW_USB_V = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_PSW_USB_SV:
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CHECK_REG_TYPE(uint32_t);
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env->PSW_USB_SV = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_PSW_USB_AV:
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CHECK_REG_TYPE(uint32_t);
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env->PSW_USB_AV = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_PSW_USB_SAV:
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CHECK_REG_TYPE(uint32_t);
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env->PSW_USB_SAV = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_SYSCON:
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CHECK_REG_TYPE(uint32_t);
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env->SYSCON = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_CPU_ID:
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CHECK_REG_TYPE(uint32_t);
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env->CPU_ID = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_BIV:
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CHECK_REG_TYPE(uint32_t);
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env->BIV = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_BTV:
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CHECK_REG_TYPE(uint32_t);
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env->BTV = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_ISP:
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CHECK_REG_TYPE(uint32_t);
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env->ISP = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_ICR:
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CHECK_REG_TYPE(uint32_t);
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env->ICR = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_FCX:
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CHECK_REG_TYPE(uint32_t);
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env->FCX = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_LCX:
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CHECK_REG_TYPE(uint32_t);
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env->LCX = *(uint32_t *)value;
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break;
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case UC_TRICORE_REG_COMPAT:
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CHECK_REG_TYPE(uint32_t);
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env->COMPAT = *(uint32_t *)value;
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break;
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}
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}
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CHECK_RET_DEPRECATE(ret, regid);
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return ret;
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}
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static int tricore_cpus_init(struct uc_struct *uc, const char *cpu_model)
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{
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TriCoreCPU *cpu;
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cpu = cpu_tricore_init(uc);
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if (cpu == NULL) {
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return -1;
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}
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return 0;
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}
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static void tricore_release(void *ctx)
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{
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int i;
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TCGContext *tcg_ctx = (TCGContext *)ctx;
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TriCoreCPU *cpu = (TriCoreCPU *)tcg_ctx->uc->cpu;
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CPUTLBDesc *d = cpu->neg.tlb.d;
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CPUTLBDescFast *f = cpu->neg.tlb.f;
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CPUTLBDesc *desc;
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CPUTLBDescFast *fast;
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release_common(ctx);
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for (i = 0; i < NB_MMU_MODES; i++) {
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desc = &(d[i]);
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fast = &(f[i]);
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g_free(desc->iotlb);
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g_free(fast->table);
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}
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}
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DEFAULT_VISIBILITY
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void uc_init(struct uc_struct *uc)
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{
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uc->reg_read = reg_read;
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uc->reg_write = reg_write;
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uc->reg_reset = reg_reset;
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uc->set_pc = tricore_set_pc;
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uc->get_pc = tricore_get_pc;
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uc->cpus_init = tricore_cpus_init;
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uc->release = tricore_release;
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uc->cpu_context_size = offsetof(CPUTriCoreState, end_reset_fields);
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uc_common_init(uc);
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}
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