Merge remote-tracking branch 'tyssjhx/dev' into loongarch-port

fix: modify the code to pass compile

add: add code for tcg_out_op, tcg_can_emit_vec_op, tcg_target_op_def to support new tcg_op

fix: fix bugs related to epilogue and ret_addr

fix: fix bug in qemu_ld_slow_path, the return register is wrong

qemu/include/tcg/tcg.h

@@ -815,9 +815,6 @@ struct TCGContext {
 
     char s390x_cpu_reg_names[16][4]; // renamed from original cpu_reg_names[][] to avoid name clash with m68k
     TCGv_i64 regs[16];
-
-    // loongarch 
-    bool use_lsx_instructions;
 };
 
 static inline size_t temp_idx(TCGContext *tcg_ctx, TCGTemp *ts)

qemu/tcg/loongarch64/tcg-target.h

@@ -97,6 +97,8 @@ typedef enum {
     TCG_VEC_TMP0 = TCG_REG_V23,
 } TCGReg;
 
+extern bool use_lsx_instructions;
+
 /* used for function call generation */
 #define TCG_REG_CALL_STACK              TCG_REG_SP
 #define TCG_TARGET_STACK_ALIGN          16
@@ -185,11 +187,10 @@ typedef enum {
 #define TCG_TARGET_HAS_mulsh_i64        1
 #define TCG_TARGET_HAS_direct_jump      0
 
-// TODO: use_lsx_instructions?
-#define TCG_TARGET_HAS_qemu_ldst_i128   1
+#define TCG_TARGET_HAS_qemu_ldst_i128   use_lsx_instructions
 
 #define TCG_TARGET_HAS_v64              0
-#define TCG_TARGET_HAS_v128             1
+#define TCG_TARGET_HAS_v128             use_lsx_instructions
 #define TCG_TARGET_HAS_v256             0
 
 #define TCG_TARGET_HAS_not_vec          1

qemu/tcg/loongarch64/tcg-target.inc.c

@@ -32,6 +32,8 @@
 #include "../tcg-ldst.inc.c"
 #include <asm/hwcap.h>
 
+bool use_lsx_instructions;
+
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
     "zero",
@@ -2602,10 +2604,10 @@ static void tcg_target_init(TCGContext *s)
     }
 
     if (hwcap & HWCAP_LOONGARCH_LSX) {
-        s->use_lsx_instructions = 1;
+        use_lsx_instructions = 1;
     }
 #else
-    s->use_lsx_instructions = 1;
+    use_lsx_instructions = 1;
 #endif
 
     s->tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;