Merge branch 'master' into m1
This commit is contained in:
Nguyen Anh Quynh
30
tests/regress/LICENSE
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30
tests/regress/LICENSE
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This is the software license for Unicorn regression tests. The regression tests
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are written by several Unicorn contributors (See CREDITS.TXT) and maintained by
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Hoang-Vu Dang <dang.hvu@gmail.com>
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Copyright (c) 2015, Unicorn contributors
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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* Neither the name of the developer(s) nor the names of its
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contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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167
tests/regress/jumping.py
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167
tests/regress/jumping.py
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#!/usr/bin/env python
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# Mariano Graziano
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from unicorn import *
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from unicorn.x86_const import *
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import regress
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#echo -ne "\x48\x31\xc0\x48\xb8\x04\x00\x00\x00\x00\x00\x00\x00\x48\x3d\x05\x00\x00\x00\x74\x05\xe9\x0f\x00\x00\x00\x48\xba\xbe\xba\x00\x00\x00\x00\x00\x00\xe9\x0f\x00\x00\x00\x48\xba\xca\xc0\x00\x00\x00\x00\x00\x00\xe9\x00\x00\x00\x00\x90" | ndisasm - -b64
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#00000000 4831C0 xor rax,rax
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#00000003 48B8040000000000 mov rax,0x4
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# -0000
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#0000000D 483D05000000 cmp rax,0x5
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#00000013 7405 jz 0x1a
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#00000015 E90F000000 jmp qword 0x29
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#0000001A 48BABEBA00000000 mov rdx,0xbabe
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# -0000
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#00000024 E90F000000 jmp qword 0x38
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#00000029 48BACAC000000000 mov rdx,0xc0ca
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# -0000
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#00000033 E900000000 jmp qword 0x38
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#00000038 90 nop
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mu = 0
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zf = 1 # (0:clear, 1:set)
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class Init(regress.RegressTest):
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def clear_zf(self):
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eflags_cur = mu.reg_read(UC_X86_REG_EFLAGS)
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eflags = eflags_cur & ~(1 << 6)
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#eflags = 0x0
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print "[clear_zf] - eflags from %x to %x" % (eflags_cur, eflags)
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if eflags != eflags_cur:
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print "[clear_zf] - writing new eflags..."
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mu.reg_write(UC_X86_REG_EFLAGS, eflags)
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def set_zf(self):
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eflags_cur = mu.reg_read(UC_X86_REG_EFLAGS)
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eflags = eflags_cur | (1 << 6)
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#eflags = 0xFFFFFFFF
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print "[set_zf] - eflags from %x to %x" % (eflags_cur, eflags)
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if eflags != eflags_cur:
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print "[set_zf] - writing new eflags..."
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mu.reg_write(UC_X86_REG_EFLAGS, eflags)
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def handle_zf(self, zf):
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print "[handle_zf] - eflags " , zf
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if zf == 0: self.clear_zf()
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else: self.set_zf()
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def multipath(self):
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print "[multipath] - handling ZF (%s) - default" % zf
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self.handle_zf(zf)
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# callback for tracing basic blocks
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def hook_block(self, uc, address, size, user_data):
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print(">>> Tracing basic block at 0x%x, block size = 0x%x" %(address, size))
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# callback for tracing instructions
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def hook_code(self, uc, address, size, user_data):
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print(">>> Tracing instruction at 0x%x, instruction size = %u" %(address, size))
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rax = mu.reg_read(UC_X86_REG_RAX)
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rbx = mu.reg_read(UC_X86_REG_RBX)
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rcx = mu.reg_read(UC_X86_REG_RCX)
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rdx = mu.reg_read(UC_X86_REG_RDX)
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rsi = mu.reg_read(UC_X86_REG_RSI)
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rdi = mu.reg_read(UC_X86_REG_RDI)
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r8 = mu.reg_read(UC_X86_REG_R8)
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r9 = mu.reg_read(UC_X86_REG_R9)
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r10 = mu.reg_read(UC_X86_REG_R10)
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r11 = mu.reg_read(UC_X86_REG_R11)
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r12 = mu.reg_read(UC_X86_REG_R12)
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r13 = mu.reg_read(UC_X86_REG_R13)
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r14 = mu.reg_read(UC_X86_REG_R14)
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r15 = mu.reg_read(UC_X86_REG_R15)
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eflags = mu.reg_read(UC_X86_REG_EFLAGS)
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print(">>> RAX = %x" %rax)
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print(">>> RBX = %x" %rbx)
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print(">>> RCX = %x" %rcx)
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print(">>> RDX = %x" %rdx)
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print(">>> RSI = %x" %rsi)
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print(">>> RDI = %x" %rdi)
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print(">>> R8 = %x" %r8)
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print(">>> R9 = %x" %r9)
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print(">>> R10 = %x" %r10)
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print(">>> R11 = %x" %r11)
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print(">>> R12 = %x" %r12)
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print(">>> R13 = %x" %r13)
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print(">>> R14 = %x" %r14)
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print(">>> R15 = %x" %r15)
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print(">>> ELAGS = %x" %eflags)
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print "-"*11
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self.multipath()
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print "-"*11
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# callback for tracing memory access (READ or WRITE)
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def hook_mem_access(self, uc, access, address, size, value, user_data):
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if access == UC_MEM_WRITE:
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print(">>> Memory is being WRITE at 0x%x, data size = %u, data value = 0x%x" \
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%(address, size, value))
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else: # READ
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print(">>> Memory is being READ at 0x%x, data size = %u" \
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%(address, size))
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# callback for tracing invalid memory access (READ or WRITE)
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def hook_mem_invalid(self, uc, access, address, size, value, user_data):
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print("[ HOOK_MEM_INVALID - Address: %s ]" % hex(address))
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if access == UC_MEM_WRITE_UNMAPPED:
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print(">>> Missing memory is being WRITE at 0x%x, data size = %u, data value = 0x%x" %(address, size, value))
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return True
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else:
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print(">>> Missing memory is being READ at 0x%x, data size = %u, data value = 0x%x" %(address, size, value))
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return True
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def hook_mem_fetch_unmapped(self, uc, access, address, size, value, user_data):
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print("[ HOOK_MEM_FETCH - Address: %s ]" % hex(address))
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print("[ mem_fetch_unmapped: faulting address at %s ]" % hex(address).strip("L"))
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return True
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def runTest(self):
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global mu
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JUMP = "\x48\x31\xc0\x48\xb8\x04\x00\x00\x00\x00\x00\x00\x00\x48\x3d\x05\x00\x00\x00\x74\x05\xe9\x0f\x00\x00\x00\x48\xba\xbe\xba\x00\x00\x00\x00\x00\x00\xe9\x0f\x00\x00\x00\x48\xba\xca\xc0\x00\x00\x00\x00\x00\x00\xe9\x00\x00\x00\x00\x90"
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ADDRESS = 0x1000000
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print("Emulate x86_64 code")
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# Initialize emulator in X86-64bit mode
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mu = Uc(UC_ARCH_X86, UC_MODE_64)
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# map 2MB memory for this emulation
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mu.mem_map(ADDRESS, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(ADDRESS, JUMP)
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# setup stack
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mu.reg_write(UC_X86_REG_RSP, ADDRESS + 0x200000)
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# tracing all basic blocks with customized callback
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mu.hook_add(UC_HOOK_BLOCK, self.hook_block)
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# tracing all instructions in range [ADDRESS, ADDRESS+0x60]
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mu.hook_add(UC_HOOK_CODE, self.hook_code, None, ADDRESS, ADDRESS+0x60)
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# tracing all memory READ & WRITE access
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mu.hook_add(UC_HOOK_MEM_WRITE, self.hook_mem_access)
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mu.hook_add(UC_HOOK_MEM_READ, self.hook_mem_access)
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mu.hook_add(UC_HOOK_MEM_FETCH_UNMAPPED, self.hook_mem_fetch_unmapped)
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mu.hook_add(UC_HOOK_MEM_READ_UNMAPPED | UC_HOOK_MEM_WRITE_UNMAPPED, self.hook_mem_invalid)
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try:
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# emulate machine code in infinite time
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mu.emu_start(ADDRESS, ADDRESS + len(JUMP))
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except UcError as e:
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print("ERROR: %s" % e)
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rdx = mu.reg_read(UC_X86_REG_RDX)
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self.assertEqual(rdx, 0xbabe, "RDX contains the wrong value. Eflags modification failed.")
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if __name__ == '__main__':
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regress.main()
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