Merge systemz to the latest uc2 codebase

2021-12-26 22:58:32 +01:00
parent cddc9cf2ed 64da57ff29
commit faa689c0f0
60 changed files with 28970 additions and 5 deletions
--- a/qemu/target/s390x/unicorn.c
+++ b/qemu/target/s390x/unicorn.c
@@ -0,0 +1,179 @@
+/* Unicorn Emulator Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015-2021 */
+
+#include "sysemu/cpus.h"
+#include "cpu.h"
+#include "unicorn_common.h"
+#include "uc_priv.h"
+#include "unicorn.h"
+
+S390CPU *cpu_s390_init(struct uc_struct *uc, const char *cpu_model);
+
+static void s390_set_pc(struct uc_struct *uc, uint64_t address)
+{
+    // ((CPUS390XState *)uc->cpu->env_ptr)->pc = address;
+}
+
+static void s390_release(void *ctx)
+{
+#if 0
+    int i;
+    TCGContext *tcg_ctx = (TCGContext *)ctx;
+    S390XCPU *cpu = (S390XCPU *)tcg_ctx->uc->cpu;
+    CPUTLBDesc *d = cpu->neg.tlb.d;
+    CPUTLBDescFast *f = cpu->neg.tlb.f;
+    CPUTLBDesc *desc;
+    CPUTLBDescFast *fast;
+
+    release_common(ctx);
+    for (i = 0; i < NB_MMU_MODES; i++) {
+        desc = &(d[i]);
+        fast = &(f[i]);
+        g_free(desc->iotlb);
+        g_free(fast->table);
+    }
+#endif
+}
+
+void s390_reg_reset(struct uc_struct *uc)
+{
+    CPUArchState *env = uc->cpu->env_ptr;
+
+    memset(env->regs, 0, sizeof(env->regs));
+    memset(env->aregs, 0, sizeof(env->aregs));
+
+    env->psw.addr = 0;
+}
+
+static void reg_read(CPUS390XState *env, unsigned int regid, void *value)
+{
+    if (regid >= UC_S390X_REG_R0 && regid <= UC_S390X_REG_R15) {
+        *(uint64_t *)value = env->regs[regid - UC_S390X_REG_R0];
+        return;
+    }
+
+    if (regid >= UC_S390X_REG_A0 && regid <= UC_S390X_REG_A15) {
+        *(uint32_t *)value = env->regs[regid - UC_S390X_REG_A0];
+        return;
+    }
+
+    switch (regid) {
+    default:
+        break;
+    case UC_S390X_REG_PC:
+        *(uint64_t *)value = env->psw.addr;
+        break;
+    }
+}
+
+static void reg_write(CPUS390XState *env, unsigned int regid, const void *value)
+{
+    if (regid >= UC_S390X_REG_R0 && regid <= UC_S390X_REG_R15) {
+        env->regs[regid - UC_S390X_REG_R0] = *(uint64_t *)value;
+        return;
+    }
+
+    if (regid >= UC_S390X_REG_A0 && regid <= UC_S390X_REG_A15) {
+        env->regs[regid - UC_S390X_REG_A0] = *(uint32_t *)value;
+        return;
+    }
+
+    switch (regid) {
+    default:
+        break;
+    case UC_S390X_REG_PC:
+        env->psw.addr = *(uint64_t *)value;
+        break;
+    }
+}
+
+static int s390_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
+                         int count)
+{
+    CPUS390XState *env = &(S390_CPU(uc->cpu)->env);
+    int i;
+
+    for (i = 0; i < count; i++) {
+        unsigned int regid = regs[i];
+        void *value = vals[i];
+        reg_read(env, regid, value);
+    }
+
+    return 0;
+}
+
+static int s390_reg_write(struct uc_struct *uc, unsigned int *regs,
+                          void *const *vals, int count)
+{
+    CPUS390XState *env = &(S390_CPU(uc->cpu)->env);
+    int i;
+
+    for (i = 0; i < count; i++) {
+        unsigned int regid = regs[i];
+        const void *value = vals[i];
+        reg_write(env, regid, value);
+        if (regid == UC_S390X_REG_PC) {
+            // force to quit execution and flush TB
+            uc->quit_request = true;
+            uc_emu_stop(uc);
+        }
+    }
+
+    return 0;
+}
+
+DEFAULT_VISIBILITY
+int s390_context_reg_read(struct uc_context *ctx, unsigned int *regs,
+                          void **vals, int count)
+{
+    CPUS390XState *env = (CPUS390XState *)ctx->data;
+    int i;
+
+    for (i = 0; i < count; i++) {
+        unsigned int regid = regs[i];
+        void *value = vals[i];
+        reg_read(env, regid, value);
+    }
+
+    return 0;
+}
+
+DEFAULT_VISIBILITY
+int s390_context_reg_write(struct uc_context *ctx, unsigned int *regs,
+                           void *const *vals, int count)
+{
+    CPUS390XState *env = (CPUS390XState *)ctx->data;
+    int i;
+
+    for (i = 0; i < count; i++) {
+        unsigned int regid = regs[i];
+        const void *value = vals[i];
+        reg_write(env, regid, value);
+    }
+
+    return 0;
+}
+
+static int s390_cpus_init(struct uc_struct *uc, const char *cpu_model)
+{
+    S390CPU *cpu;
+
+    cpu = cpu_s390_init(uc, cpu_model);
+    if (cpu == NULL) {
+        return -1;
+    }
+    return 0;
+}
+
+DEFAULT_VISIBILITY
+void s390_uc_init(struct uc_struct *uc)
+{
+    uc->release = s390_release;
+    uc->reg_read = s390_reg_read;
+    uc->reg_write = s390_reg_write;
+    uc->reg_reset = s390_reg_reset;
+    uc->set_pc = s390_set_pc;
+    uc->cpus_init = s390_cpus_init;
+    uc->cpu_context_size = offsetof(CPUS390XState, end_reset_fields);
+    uc_common_init(uc);
+}