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Python bindings: Fix editable install + Execute Python2.7 workflow tests (#2044)

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* Python binding:
- Added missing `license` field in pyproject.toml file
- Fixed editable mode install and some more code cleanup in setup.py
- Refreshed README.md
- Replaced f-string formatter in tests with `format` method in order to be py2-compatible
- Fixed typos
- PEP8 fixes

* GitHub Action: Install Python2.7 and run tests for re-tagged wheels on native arch runners only

* Python bindings:
- Use #x formatter to format hex values
This commit is contained in:
@Antelox
2024-12-07 07:52:21 +01:00
committed by GitHub
parent 3a01515367
commit f78a3f2f59
10 changed files with 152 additions and 114 deletions
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5
bindings/python/tests/test_arm64.py
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@@ -87,7 +87,8 @@ def test_arm64_read_sctlr():
def test_arm64_hook_mrs():
def _hook_mrs(uc, reg, cp_reg, _):
print(f">>> Hook MRS instruction: reg = 0x{reg:x}(UC_ARM64_REG_X2) cp_reg = {cp_reg}")
print(">>> Hook MRS instruction: reg = {reg:#x}(UC_ARM64_REG_X2) cp_reg = {cp_reg}".format(reg=reg,
cp_reg=cp_reg))
uc.reg_write(reg, 0x114514)
print(">>> Write 0x114514 to X")
@@ -111,7 +112,7 @@ def test_arm64_hook_mrs():
# Start emulation
mu.emu_start(0x1000, 0x1000 + len(ARM64_MRS_CODE))
print(f">>> X2 = {mu.reg_read(UC_ARM64_REG_X2):x}")
print(">>> X2 = {reg:#x}".format(reg=mu.reg_read(UC_ARM64_REG_X2)))
except UcError as e:
print("ERROR: %s" % e)

25
bindings/python/tests/test_ctl.py
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@@ -2,6 +2,8 @@
# Sample code for Unicorn.
# By Lazymio(@wtdcode), 2021
import pytest
import sys
from unicorn import *
from unicorn.x86_const import *
from datetime import datetime
@@ -20,7 +22,9 @@ def test_uc_ctl_read():
timeout = uc.ctl_get_timeout()
print(f">>> arch={arch} mode={mode} page size={page_size} timeout={timeout}")
print(">>> arch={arch} mode={mode} page size={page_size} timeout={timeout}".format(arch=arch, mode=mode,
page_size=page_size,
timeout=timeout))
def time_emulation(uc, start, end):
@@ -31,6 +35,8 @@ def time_emulation(uc, start, end):
return (datetime.now() - n).total_seconds() * 1e6
# TODO: Check if worth adapting the ctl_request_cache method for py2 bindings
@pytest.mark.skipif(sys.version_info < (3, 7), reason="requires python3.7 or higher")
def test_uc_ctl_tb_cache():
# Initialize emulator in X86-32bit mode
uc = Uc(UC_ARCH_X86, UC_MODE_32)
@@ -52,7 +58,7 @@ def test_uc_ctl_tb_cache():
# Now we request cache for all TBs.
for i in range(8):
tb = uc.ctl_request_cache(addr + i * 512)
print(f">>> TB is cached at {hex(tb[0])} which has {tb[1]} instructions with {tb[2]} bytes")
print(">>> TB is cached at {:#x} which has {} instructions with {} bytes".format(tb[0], tb[1], tb[2]))
# Do emulation with all TB cached.
cached = time_emulation(uc, addr, addr + len(code))
@@ -63,17 +69,22 @@ def test_uc_ctl_tb_cache():
evicted = time_emulation(uc, addr, addr + len(code))
print(f">>> Run time: First time {standard}, Cached: {cached}, Cached evicted: {evicted}")
print(">>> Run time: First time {standard}, Cached: {cached}, Cached evicted: {evicted}".format(standard=standard,
cached=cached,
evicted=evicted))
def trace_new_edge(uc, cur, prev, data):
print(f">>> Getting a new edge from {hex(prev.pc + prev.size - 1)} to {hex(cur.pc)}")
print(">>> Getting a new edge from {:#x} to {:#x}".format(prev.pc + prev.size - 1, cur.pc))
def trace_tcg_sub(uc, address, arg1, arg2, size, data):
print(f">>> Get a tcg sub opcode at {hex(address)} with args: {arg1} and {arg2}")
print(">>> Get a tcg sub opcode at {address:#x} with args: {arg1} and {arg2}".format(address=address, arg1=arg1,
arg2=arg2))
# TODO: Check if worth adapting the hook_add method for py2 bindings
@pytest.mark.skipif(sys.version_info < (3, 7), reason="requires python3.7 or higher")
def test_uc_ctl_exits():
uc = Uc(UC_ARCH_X86, UC_MODE_32)
addr = 0x1000
@@ -110,7 +121,7 @@ def test_uc_ctl_exits():
eax = uc.reg_read(UC_X86_REG_EAX)
ebx = uc.reg_read(UC_X86_REG_EBX)
print(f">>> eax = {hex(eax)} and ebx = {hex(ebx)} after the first emulation")
print(">>> eax = {eax:#x} and ebx = {ebx:#x} after the first emulation".format(eax=eax, ebx=ebx))
# This should stop at ADDRESS + 8, even though we don't provide an exit.
uc.emu_start(addr, 0)
@@ -118,7 +129,7 @@ def test_uc_ctl_exits():
eax = uc.reg_read(UC_X86_REG_EAX)
ebx = uc.reg_read(UC_X86_REG_EBX)
print(f">>> eax = {hex(eax)} and ebx = {hex(ebx)} after the first emulation")
print(">>> eax = {eax:#x} and ebx = {ebx:#x} after the first emulation".format(eax=eax, ebx=ebx))
if __name__ == "__main__":

2
bindings/python/tests/test_network_auditing.py
View File

@@ -356,7 +356,7 @@ def hook_intr(uc, intno, user_data):
fd = args[0]
how = args[1]
msg = "fd(%d) is shutted down because of %d" % (fd, how)
msg = "fd(%d) is shut down because of %d" % (fd, how)
fd_chains.add_log(fd, msg)
print_sockcall(msg)

9
bindings/python/tests/test_x86.py
View File

@@ -639,13 +639,16 @@ def test_x86_16():
def mmio_read_cb(uc, offset, size, data):
print(f">>> Read IO memory at offset {hex(offset)} with {hex(size)} bytes and return 0x19260817")
print(">>> Read IO memory at offset {offset:#x} with {size:#x} bytes and return 0x19260817".format(offset=offset,
size=size))
return 0x19260817
def mmio_write_cb(uc, offset, size, value, data):
print(f">>> Write value {hex(value)} to IO memory at offset {hex(offset)} with {hex(size)} bytes")
print(">>> Write value {value:#x} to IO memory at offset {offset:#x} with {size:#x} bytes".format(value=value,
offset=offset,
size=size))
def test_i386_mmio():
@@ -668,7 +671,7 @@ def test_i386_mmio():
mu.emu_start(0x10000, 0x10000 + len(X86_MMIO_CODE))
# now print out some registers
print(f">>> Emulation done. ECX={hex(mu.reg_read(UC_X86_REG_ECX))}")
print(">>> Emulation done. ECX={reg:#x}".format(reg=mu.reg_read(UC_X86_REG_ECX)))
except UcError as e:
print("ERROR: %s" % e)