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bindings: update to support X86 MSR id

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This commit is contained in:
Nguyen Anh Quynh
2017-02-24 21:51:01 +08:00
parent fc72622ba8
commit f4325f8c4e
6 changed files with 14 additions and 9 deletions
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3
bindings/dotnet/UnicornManaged/Const/X86.fs
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@@ -257,7 +257,8 @@ module X86 =
let UC_X86_REG_TR = 245
let UC_X86_REG_FPCW = 246
let UC_X86_REG_FPTAG = 247
let UC_X86_REG_ENDING = 248
let UC_X86_REG_MSR = 248
let UC_X86_REG_ENDING = 249
// X86 instructions

3
bindings/go/unicorn/x86_const.go
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@@ -252,7 +252,8 @@ const (
X86_REG_TR = 245
X86_REG_FPCW = 246
X86_REG_FPTAG = 247
X86_REG_ENDING = 248
X86_REG_MSR = 248
X86_REG_ENDING = 249
// X86 instructions

3
bindings/java/unicorn/X86Const.java
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@@ -254,7 +254,8 @@ public interface X86Const {
public static final int UC_X86_REG_TR = 245;
public static final int UC_X86_REG_FPCW = 246;
public static final int UC_X86_REG_FPTAG = 247;
public static final int UC_X86_REG_ENDING = 248;
public static final int UC_X86_REG_MSR = 248;
public static final int UC_X86_REG_ENDING = 249;
// X86 instructions

4
bindings/python/unicorn/unicorn.py
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@@ -357,11 +357,11 @@ class Uc(object):
if status != uc.UC_ERR_OK:
raise UcError(status)
# read from MSR
# read from MSR - X86 only
def msr_read(self, msr_id):
return self.reg_read(x86_const.UC_X86_REG_MSR, msr_id)
# write to MSR
# write to MSR - X86 only
def msr_write(self, msr_id, value):
return self.reg_write(x86_const.UC_X86_REG_MSR, (msr_id, value))

3
bindings/ruby/unicorn_gem/lib/unicorn/x86_const.rb
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@@ -252,7 +252,8 @@ module Unicorn
UC_X86_REG_TR = 245
UC_X86_REG_FPCW = 246
UC_X86_REG_FPTAG = 247
UC_X86_REG_ENDING = 248
UC_X86_REG_MSR = 248
UC_X86_REG_ENDING = 249
# X86 instructions