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feat(rust): improve ARM CP register ergonomics (#2160)

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This commit is contained in:
Amaan Qureshi
2025-04-12 22:36:24 -04:00
committed by GitHub
parent 1b98fec009
commit f0bdeb5a74
7 changed files with 184 additions and 51 deletions
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35
bindings/rust/src/tests/arm.rs
View File

@@ -1,5 +1,5 @@
use super::*;
use crate::{ArmCpuModel, RegisterARM, RegisterARM_CP, TcgOpCode, TcgOpFlag, uc_error};
use crate::{ArmCpuModel, RegisterARM, RegisterARMCP, TcgOpCode, TcgOpFlag, uc_error};
#[test]
fn test_arm_nop() {
@@ -600,16 +600,7 @@ fn test_arm_mem_access_abort() {
#[test]
fn test_arm_read_sctlr() {
let uc = Unicorn::new(Arch::ARM, Mode::ARM).unwrap();
let mut reg = RegisterARM_CP {
cp: 15,
is64: 0,
sec: 0,
crn: 1,
crm: 0,
opc1: 0,
opc2: 0,
val: 0,
};
let mut reg = RegisterARMCP::new().cp(15).crn(1);
uc.reg_read_arm_coproc(&mut reg).unwrap();
assert_eq!((reg.val >> 31) & 1, 0);
}
@@ -620,16 +611,7 @@ fn test_arm_be_cpsr_sctlr() {
uc.ctl_set_cpu_model(ArmCpuModel::Model_1176 as i32)
.unwrap();
let mut reg = RegisterARM_CP {
cp: 15,
is64: 0,
sec: 0,
crn: 1,
crm: 0,
opc1: 0,
opc2: 0,
val: 0,
};
let mut reg = RegisterARMCP::new().cp(15).crn(1);
uc.reg_read_arm_coproc(&mut reg).unwrap();
let cpsr = uc.reg_read(RegisterARM::CPSR).unwrap();
@@ -640,16 +622,7 @@ fn test_arm_be_cpsr_sctlr() {
uc.ctl_set_cpu_model(ArmCpuModel::CORTEX_A15 as i32)
.unwrap();
let mut reg = RegisterARM_CP {
cp: 15,
is64: 0,
sec: 0,
crn: 1,
crm: 0,
opc1: 0,
opc2: 0,
val: 0,
};
let mut reg = RegisterARMCP::new().cp(15).crn(1);
uc.reg_read_arm_coproc(&mut reg).unwrap();
let cpsr = uc.reg_read(RegisterARM::CPSR).unwrap();

5
bindings/rust/src/tests/arm64.rs
View File

@@ -1,4 +1,4 @@
use unicorn_engine_sys::{Arm64CpuModel, Arm64Insn, RegisterARM64};
use unicorn_engine_sys::{Arm64CpuModel, Arm64Insn, RegisterARM64, RegisterARM64CP};
use super::*;
@@ -142,7 +142,8 @@ fn test_arm64_v8_pac() {
fn test_arm64_read_sctlr() {
let uc = Unicorn::new(Arch::ARM64, Mode::ARM | Mode::LITTLE_ENDIAN).unwrap();
let reg = uc.reg_read_arm64_coproc().unwrap();
let mut reg = RegisterARM64CP::new().crn(1).op0(0b11);
uc.reg_read_arm64_coproc(&mut reg).unwrap();
assert_eq!(reg.val >> 58, 0);
}

1
bindings/rust/src/tests/ppc.rs
View File

@@ -25,7 +25,6 @@ fn test_ppc32_add() {
// https://www.ibm.com/docs/en/aix/7.2?topic=set-fadd-fa-floating-add-instruction
#[test]
// #[ignore = "Crashes on Windows & some Linux distros"]
fn test_ppc32_fadd() {
let code = [
0xfc, 0xc4, 0x28, 0x2a, // fadd 6, 4, 5