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Merge branch 'master' into msvc2

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This commit is contained in:
Nguyen Anh Quynh
2017-04-21 01:17:00 +08:00
parent 094ca80092 5dbc640b9a
commit e917c9de10
16 changed files with 54 additions and 19 deletions
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17
qemu/target-arm/translate.c
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@@ -10418,14 +10418,27 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) // qq
}
}
insn = arm_lduw_code(env, s->pc, s->bswap_code);
// Unicorn: trace this instruction on request
if (HOOK_EXISTS_BOUNDED(s->uc, UC_HOOK_CODE, s->pc)) {
gen_uc_tracecode(tcg_ctx, 2, UC_HOOK_CODE_IDX, s->uc, s->pc);
// determine instruction size (Thumb/Thumb2)
switch(insn & 0xf800) {
// Thumb2: 32-bit
case 0xe800:
case 0xf000:
case 0xf800:
gen_uc_tracecode(tcg_ctx, 4, UC_HOOK_CODE_IDX, s->uc, s->pc);
break;
// Thumb: 16-bit
default:
gen_uc_tracecode(tcg_ctx, 2, UC_HOOK_CODE_IDX, s->uc, s->pc);
break;
}
// the callback might want to stop emulation immediately
check_exit_request(tcg_ctx);
}
insn = arm_lduw_code(env, s->pc, s->bswap_code);
s->pc += 2;
switch (insn >> 12) {

6
qemu/target-arm/unicorn_aarch64.c
View File

@@ -88,6 +88,9 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
case UC_ARM64_REG_SP:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[31];
break;
case UC_ARM64_REG_NZCV:
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV;
break;
}
}
}
@@ -141,6 +144,9 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
case UC_ARM64_REG_SP:
ARM_CPU(uc, mycpu)->env.xregs[31] = *(uint64_t *)value;
break;
case UC_ARM64_REG_NZCV:
cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *) value, CPSR_NZCV);
break;
}
}
}