Add clang-format and format code to qemu code style
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@@ -37,7 +37,6 @@ static void mips_set_pc(struct uc_struct *uc, uint64_t address)
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((CPUMIPSState *)uc->cpu->env_ptr)->active_tc.PC = address;
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}
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static void mips_release(void *ctx)
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{
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int i;
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@@ -75,20 +74,21 @@ static void reg_read(CPUMIPSState *env, unsigned int regid, void *value)
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
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*(mipsreg_t *)value = env->active_tc.gpr[regid - UC_MIPS_REG_0];
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else {
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switch(regid) {
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default: break;
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case UC_MIPS_REG_PC:
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*(mipsreg_t *)value = env->active_tc.PC;
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break;
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case UC_MIPS_REG_CP0_CONFIG3:
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*(mipsreg_t *)value = env->CP0_Config3;
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break;
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case UC_MIPS_REG_CP0_STATUS:
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*(mipsreg_t *)value = env->CP0_Status;
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break;
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case UC_MIPS_REG_CP0_USERLOCAL:
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*(mipsreg_t *)value = env->active_tc.CP0_UserLocal;
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break;
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switch (regid) {
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default:
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break;
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case UC_MIPS_REG_PC:
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*(mipsreg_t *)value = env->active_tc.PC;
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break;
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case UC_MIPS_REG_CP0_CONFIG3:
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*(mipsreg_t *)value = env->CP0_Config3;
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break;
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case UC_MIPS_REG_CP0_STATUS:
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*(mipsreg_t *)value = env->CP0_Status;
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break;
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case UC_MIPS_REG_CP0_USERLOCAL:
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*(mipsreg_t *)value = env->active_tc.CP0_UserLocal;
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break;
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}
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}
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@@ -100,31 +100,33 @@ static void reg_write(CPUMIPSState *env, unsigned int regid, const void *value)
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
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env->active_tc.gpr[regid - UC_MIPS_REG_0] = *(mipsreg_t *)value;
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else {
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switch(regid) {
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default: break;
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case UC_MIPS_REG_PC:
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env->active_tc.PC = *(mipsreg_t *)value;
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break;
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case UC_MIPS_REG_CP0_CONFIG3:
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env->CP0_Config3 = *(mipsreg_t *)value;
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break;
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case UC_MIPS_REG_CP0_STATUS:
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// TODO: ALL CP0 REGS
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// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00090-2B-MIPS32PRA-AFP-06.02.pdf
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// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00582-2B-microMIPS32-AFP-05.04.pdf
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env->CP0_Status = *(mipsreg_t *)value;
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compute_hflags(env);
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break;
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case UC_MIPS_REG_CP0_USERLOCAL:
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env->active_tc.CP0_UserLocal = *(mipsreg_t *)value;
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break;
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switch (regid) {
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default:
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break;
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case UC_MIPS_REG_PC:
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env->active_tc.PC = *(mipsreg_t *)value;
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break;
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case UC_MIPS_REG_CP0_CONFIG3:
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env->CP0_Config3 = *(mipsreg_t *)value;
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break;
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case UC_MIPS_REG_CP0_STATUS:
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// TODO: ALL CP0 REGS
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// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00090-2B-MIPS32PRA-AFP-06.02.pdf
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// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00582-2B-microMIPS32-AFP-05.04.pdf
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env->CP0_Status = *(mipsreg_t *)value;
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compute_hflags(env);
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break;
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case UC_MIPS_REG_CP0_USERLOCAL:
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env->active_tc.CP0_UserLocal = *(mipsreg_t *)value;
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break;
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}
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}
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return;
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}
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int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
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int count)
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{
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CPUMIPSState *env = &(MIPS_CPU(uc->cpu)->env);
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int i;
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@@ -138,7 +140,8 @@ int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int cou
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return 0;
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}
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int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count)
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int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
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int count)
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{
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CPUMIPSState *env = &(MIPS_CPU(uc->cpu)->env);
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int i;
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@@ -147,7 +150,7 @@ int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
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unsigned int regid = regs[i];
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const void *value = vals[i];
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reg_write(env, regid, value);
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if(regid == UC_MIPS_REG_PC){
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if (regid == UC_MIPS_REG_PC) {
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc_emu_stop(uc);
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@@ -160,15 +163,19 @@ int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
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DEFAULT_VISIBILITY
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#ifdef TARGET_MIPS64
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#ifdef TARGET_WORDS_BIGENDIAN
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int mips64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
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int mips64_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void **vals, int count)
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#else
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int mips64el_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
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int mips64el_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void **vals, int count)
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#endif
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#else // if TARGET_MIPS
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#ifdef TARGET_WORDS_BIGENDIAN
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int mips_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
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int mips_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void **vals, int count)
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#else
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int mipsel_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
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int mipsel_context_reg_read(struct uc_context *ctx, unsigned int *regs,
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void **vals, int count)
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#endif
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#endif
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{
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@@ -187,15 +194,19 @@ DEFAULT_VISIBILITY
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DEFAULT_VISIBILITY
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#ifdef TARGET_MIPS64
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#ifdef TARGET_WORDS_BIGENDIAN
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int mips64_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count)
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int mips64_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, int count)
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#else
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int mips64el_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count)
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int mips64el_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, int count)
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#endif
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#else // if TARGET_MIPS
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#ifdef TARGET_WORDS_BIGENDIAN
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int mips_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count)
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int mips_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, int count)
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#else
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int mipsel_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count)
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int mipsel_context_reg_write(struct uc_context *ctx, unsigned int *regs,
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void *const *vals, int count)
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#endif
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#endif
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{
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@@ -226,15 +237,15 @@ static int mips_cpus_init(struct uc_struct *uc, const char *cpu_model)
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DEFAULT_VISIBILITY
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#ifdef TARGET_MIPS64
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#ifdef TARGET_WORDS_BIGENDIAN
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void mips64_uc_init(struct uc_struct* uc)
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void mips64_uc_init(struct uc_struct *uc)
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#else
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void mips64el_uc_init(struct uc_struct* uc)
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void mips64el_uc_init(struct uc_struct *uc)
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#endif
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#else // if TARGET_MIPS
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#ifdef TARGET_WORDS_BIGENDIAN
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void mips_uc_init(struct uc_struct* uc)
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void mips_uc_init(struct uc_struct *uc)
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#else
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void mipsel_uc_init(struct uc_struct* uc)
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void mipsel_uc_init(struct uc_struct *uc)
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#endif
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#endif
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{
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