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updated gdtr/idtr/ldtr/tr read/write code

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This commit is contained in:
Chris Eagle
2016-02-04 16:44:52 -08:00
parent 9977054a15
commit e59382e030
4 changed files with 120 additions and 155 deletions
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192
qemu/target-i386/unicorn.c Normal file → Executable file
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@@ -277,41 +277,25 @@ int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
case UC_X86_REG_GS:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
break;
case UC_X86_REG_IDTR_LIMIT:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.idt.limit);
case UC_X86_REG_IDTR:
((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit;
((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.idt.base;
break;
case UC_X86_REG_IDTR_BASE:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.idt.base;
case UC_X86_REG_GDTR:
((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit;
((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.gdt.base;
break;
case UC_X86_REG_GDTR_LIMIT:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.gdt.limit);
case UC_X86_REG_LDTR:
((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit;
((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.ldt.base;
((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector;
((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags;
break;
case UC_X86_REG_GDTR_BASE:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.gdt.base;
break;
case UC_X86_REG_LDTR_SS:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.ldt.selector);
break;
case UC_X86_REG_LDTR_LIMIT:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.ldt.limit;
break;
case UC_X86_REG_LDTR_BASE:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.ldt.base;
break;
case UC_X86_REG_LDTR_ATTR:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.ldt.flags;
break;
case UC_X86_REG_TR_SS:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.tr.selector);
break;
case UC_X86_REG_TR_LIMIT:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.tr.limit;
break;
case UC_X86_REG_TR_BASE:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.tr.base;
break;
case UC_X86_REG_TR_ATTR:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.tr.flags;
case UC_X86_REG_TR:
((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit;
((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.tr.base;
((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector;
((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags;
break;
}
break;
@@ -561,41 +545,25 @@ int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
case UC_X86_REG_R15B:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15]);
break;
case UC_X86_REG_IDTR_LIMIT:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.idt.limit);
case UC_X86_REG_IDTR:
((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit;
((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.idt.base;
break;
case UC_X86_REG_IDTR_BASE:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.idt.base;
case UC_X86_REG_GDTR:
((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit;
((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.gdt.base;
break;
case UC_X86_REG_GDTR_LIMIT:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.gdt.limit);
case UC_X86_REG_LDTR:
((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit;
((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.ldt.base;
((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector;
((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags;
break;
case UC_X86_REG_GDTR_BASE:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.gdt.base;
break;
case UC_X86_REG_LDTR_SS:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.ldt.selector);
break;
case UC_X86_REG_LDTR_LIMIT:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.ldt.limit;
break;
case UC_X86_REG_LDTR_BASE:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.ldt.base;
break;
case UC_X86_REG_LDTR_ATTR:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.ldt.flags;
break;
case UC_X86_REG_TR_SS:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.tr.selector);
break;
case UC_X86_REG_TR_LIMIT:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.tr.limit;
break;
case UC_X86_REG_TR_BASE:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.tr.base;
break;
case UC_X86_REG_TR_ATTR:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.tr.flags;
case UC_X86_REG_TR:
((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit;
((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.tr.base;
((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector;
((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags;
break;
}
break;
@@ -756,41 +724,25 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint32_t *)value;
break;
case UC_X86_REG_IDTR_LIMIT:
WRITE_WORD(X86_CPU(uc, mycpu)->env.idt.limit, *(uint16_t *)value);
case UC_X86_REG_IDTR:
X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((SegmentCache *)value)->limit;
X86_CPU(uc, mycpu)->env.idt.base = (uint32_t)((SegmentCache *)value)->base;
break;
case UC_X86_REG_IDTR_BASE:
X86_CPU(uc, mycpu)->env.idt.base = *(uint32_t *)value;
case UC_X86_REG_GDTR:
X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((SegmentCache *)value)->limit;
X86_CPU(uc, mycpu)->env.gdt.base = (uint32_t)((SegmentCache *)value)->base;
break;
case UC_X86_REG_GDTR_LIMIT:
WRITE_WORD(X86_CPU(uc, mycpu)->env.gdt.limit, *(uint16_t *)value);
case UC_X86_REG_LDTR:
X86_CPU(uc, mycpu)->env.ldt.limit = ((SegmentCache *)value)->limit;
X86_CPU(uc, mycpu)->env.ldt.base = (uint32_t)((SegmentCache *)value)->base;
X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((SegmentCache *)value)->selector;
X86_CPU(uc, mycpu)->env.ldt.flags = ((SegmentCache *)value)->flags;
break;
case UC_X86_REG_GDTR_BASE:
X86_CPU(uc, mycpu)->env.gdt.base = *(uint32_t *)value;
break;
case UC_X86_REG_LDTR_SS:
WRITE_WORD(X86_CPU(uc, mycpu)->env.ldt.selector, *(uint16_t *)value);
break;
case UC_X86_REG_LDTR_LIMIT:
X86_CPU(uc, mycpu)->env.ldt.limit = *(uint32_t *)value;
break;
case UC_X86_REG_LDTR_BASE:
X86_CPU(uc, mycpu)->env.ldt.base = *(uint32_t *)value;
break;
case UC_X86_REG_LDTR_ATTR:
X86_CPU(uc, mycpu)->env.ldt.flags = *(uint32_t *)value;
break;
case UC_X86_REG_TR_SS:
WRITE_WORD(X86_CPU(uc, mycpu)->env.tr.selector, *(uint16_t *)value);
break;
case UC_X86_REG_TR_LIMIT:
X86_CPU(uc, mycpu)->env.tr.limit = *(uint32_t *)value;
break;
case UC_X86_REG_TR_BASE:
X86_CPU(uc, mycpu)->env.tr.base = *(uint32_t *)value;
break;
case UC_X86_REG_TR_ATTR:
X86_CPU(uc, mycpu)->env.tr.flags = *(uint32_t *)value;
case UC_X86_REG_TR:
X86_CPU(uc, mycpu)->env.tr.limit = ((SegmentCache *)value)->limit;
X86_CPU(uc, mycpu)->env.tr.base = (uint32_t)((SegmentCache *)value)->base;
X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((SegmentCache *)value)->selector;
X86_CPU(uc, mycpu)->env.tr.flags = ((SegmentCache *)value)->flags;
break;
}
break;
@@ -1050,41 +1002,25 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
case UC_X86_REG_R15B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(uint8_t *)value);
break;
case UC_X86_REG_IDTR_LIMIT:
WRITE_WORD(X86_CPU(uc, mycpu)->env.idt.limit, *(uint16_t *)value);
case UC_X86_REG_IDTR:
X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((SegmentCache *)value)->limit;
X86_CPU(uc, mycpu)->env.idt.base = ((SegmentCache *)value)->base;
break;
case UC_X86_REG_IDTR_BASE:
X86_CPU(uc, mycpu)->env.idt.base = *(uint64_t *)value;
case UC_X86_REG_GDTR:
X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((SegmentCache *)value)->limit;
X86_CPU(uc, mycpu)->env.gdt.base = ((SegmentCache *)value)->base;
break;
case UC_X86_REG_GDTR_LIMIT:
WRITE_WORD(X86_CPU(uc, mycpu)->env.gdt.limit, *(uint16_t *)value);
case UC_X86_REG_LDTR:
X86_CPU(uc, mycpu)->env.ldt.limit = ((SegmentCache *)value)->limit;
X86_CPU(uc, mycpu)->env.ldt.base = ((SegmentCache *)value)->base;
X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((SegmentCache *)value)->selector;
X86_CPU(uc, mycpu)->env.ldt.flags = ((SegmentCache *)value)->flags;
break;
case UC_X86_REG_GDTR_BASE:
X86_CPU(uc, mycpu)->env.gdt.base = *(uint64_t *)value;
break;
case UC_X86_REG_LDTR_SS:
WRITE_WORD(X86_CPU(uc, mycpu)->env.ldt.selector, *(uint16_t *)value);
break;
case UC_X86_REG_LDTR_LIMIT:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.ldt.limit, *(uint32_t *)value);
break;
case UC_X86_REG_LDTR_BASE:
X86_CPU(uc, mycpu)->env.ldt.base = *(uint64_t *)value;
break;
case UC_X86_REG_LDTR_ATTR:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.ldt.flags, *(uint32_t *)value);
break;
case UC_X86_REG_TR_SS:
WRITE_WORD(X86_CPU(uc, mycpu)->env.tr.selector, *(uint16_t *)value);
break;
case UC_X86_REG_TR_LIMIT:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.tr.limit, *(uint32_t *)value);
break;
case UC_X86_REG_TR_BASE:
X86_CPU(uc, mycpu)->env.tr.base = *(uint64_t *)value;
break;
case UC_X86_REG_TR_ATTR:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.tr.flags, *(uint32_t *)value);
case UC_X86_REG_TR:
X86_CPU(uc, mycpu)->env.tr.limit = ((SegmentCache *)value)->limit;
X86_CPU(uc, mycpu)->env.tr.base = ((SegmentCache *)value)->base;
X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((SegmentCache *)value)->selector;
X86_CPU(uc, mycpu)->env.tr.flags = ((SegmentCache *)value)->flags;
break;
}
break;