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Merging with current msvc.

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This commit is contained in:
xorstream
2017-01-23 01:07:06 +11:00
parent 72a497bc14 206819bd98
commit e46f86c80b
64 changed files with 279 additions and 801 deletions
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80
qemu/target-i386/translate.c
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@@ -1000,38 +1000,38 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
t1 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false);
t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, false);
add_sub:
return ccprepare_make(TCG_COND_LTU, t0,t1, 0,-1, true,false);
return ccprepare_make(TCG_COND_LTU, t0, t1, 0, -1, true, false);
case CC_OP_LOGICB: case CC_OP_LOGICW: case CC_OP_LOGICL: case CC_OP_LOGICQ:
case CC_OP_CLR:
return ccprepare_make(TCG_COND_NEVER, 0,0, 0,-1, false,false);
return ccprepare_make(TCG_COND_NEVER, 0, 0, 0, -1, false, false);
case CC_OP_INCB: case CC_OP_INCW: case CC_OP_INCL: case CC_OP_INCQ:
case CC_OP_DECB: case CC_OP_DECW: case CC_OP_DECL: case CC_OP_DECQ:
return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,-1, false,true );
return ccprepare_make(TCG_COND_NE, cpu_cc_src, 0, 0, -1, false, true);
case CC_OP_SHLB: case CC_OP_SHLW: case CC_OP_SHLL: case CC_OP_SHLQ:
/* (CC_SRC >> (DATA_BITS - 1)) & 1 */
size = s->cc_op - CC_OP_SHLB;
shift = (8 << size) - 1;
return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,(target_ulong)(1 << shift), false,false);
return ccprepare_make(TCG_COND_NE, cpu_cc_src, 0, 0, (target_ulong)(1 << shift), false, false);
case CC_OP_MULB: case CC_OP_MULW: case CC_OP_MULL: case CC_OP_MULQ:
return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,-1, false,false );
return ccprepare_make(TCG_COND_NE, cpu_cc_src, 0, 0, -1, false, false);
case CC_OP_BMILGB: case CC_OP_BMILGW: case CC_OP_BMILGL: case CC_OP_BMILGQ:
size = s->cc_op - CC_OP_BMILGB;
t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_src, size, false);
return ccprepare_make(TCG_COND_EQ, t0,0, 0,-1, false,false);
return ccprepare_make(TCG_COND_EQ, t0, 0, 0, -1, false, false);
case CC_OP_ADCX:
case CC_OP_ADCOX:
return ccprepare_make(TCG_COND_NE, cpu_cc_dst,0, 0,-1, false,true);
return ccprepare_make(TCG_COND_NE, cpu_cc_dst, 0, 0, -1, false, true);
case CC_OP_EFLAGS:
case CC_OP_SARB: case CC_OP_SARW: case CC_OP_SARL: case CC_OP_SARQ:
/* CC_SRC & 1 */
return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_C, false,false);
return ccprepare_make(TCG_COND_NE, cpu_cc_src, 0, 0, CC_C, false, false);
default:
/* The need to compute only C from CC_OP_DYNAMIC is important
@@ -1039,7 +1039,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
gen_update_cc_op(s);
gen_helper_cc_compute_c(tcg_ctx, reg, cpu_cc_dst, cpu_cc_src,
cpu_cc_src2, cpu_cc_op);
return ccprepare_make(TCG_COND_NE, reg,0, 0,-1, false,true);
return ccprepare_make(TCG_COND_NE, reg, 0, 0, -1, false, true);
}
}
@@ -1050,7 +1050,7 @@ static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg)
TCGv cpu_cc_src = *(TCGv *)tcg_ctx->cpu_cc_src;
gen_compute_eflags(s);
return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_P, false,false);
return ccprepare_make(TCG_COND_NE, cpu_cc_src, 0, 0, CC_P, false, false);
}
/* compute eflags.S to reg */
@@ -1068,14 +1068,14 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
case CC_OP_ADCX:
case CC_OP_ADOX:
case CC_OP_ADCOX:
return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_S, false,false);
return ccprepare_make(TCG_COND_NE, cpu_cc_src, 0, 0, CC_S, false, false);
case CC_OP_CLR:
return ccprepare_make(TCG_COND_NEVER, 0,0, 0,-1, false,false);
return ccprepare_make(TCG_COND_NEVER, 0, 0, 0, -1, false, false);
default:
{
TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, true);
return ccprepare_make(TCG_COND_LT, t0,0, 0,-1, false,false);
return ccprepare_make(TCG_COND_LT, t0, 0, 0, -1, false, false);
}
}
}
@@ -1090,12 +1090,12 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
switch (s->cc_op) {
case CC_OP_ADOX:
case CC_OP_ADCOX:
return ccprepare_make(TCG_COND_NE, cpu_cc_src2,0, 0,-1, false,true);
return ccprepare_make(TCG_COND_NE, cpu_cc_src2, 0, 0, -1, false, true);
case CC_OP_CLR:
return ccprepare_make(TCG_COND_NEVER, 0,0, 0,-1, false,false);
return ccprepare_make(TCG_COND_NEVER, 0, 0, 0, -1, false, false);
default:
gen_compute_eflags(s);
return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_O, false,false );
return ccprepare_make(TCG_COND_NE, cpu_cc_src, 0, 0, CC_O, false, false);
}
}
@@ -1114,14 +1114,14 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
case CC_OP_ADCX:
case CC_OP_ADOX:
case CC_OP_ADCOX:
return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_Z, false,false);
return ccprepare_make(TCG_COND_NE, cpu_cc_src, 0, 0, CC_Z, false, false);
case CC_OP_CLR:
return ccprepare_make(TCG_COND_ALWAYS, 0,0, 0,-1, false,false);
return ccprepare_make(TCG_COND_ALWAYS, 0, 0, 0, -1, false, false);
default:
{
TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;
TCGv t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, false);
return ccprepare_make(TCG_COND_EQ, t0,0, 0,-1, false,false);
return ccprepare_make(TCG_COND_EQ, t0, 0, 0, -1, false, false);
}
}
}
@@ -1152,7 +1152,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
tcg_gen_mov_tl(tcg_ctx, cpu_tmp4, cpu_cc_srcT);
gen_extu(tcg_ctx, size, cpu_tmp4);
t0 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false);
cc = ccprepare_make(TCG_COND_LEU, cpu_tmp4,t0, 0,-1, true,false);
cc = ccprepare_make(TCG_COND_LEU, cpu_tmp4, t0, 0, -1, true, false);
break;
case JCC_L:
@@ -1164,7 +1164,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
tcg_gen_mov_tl(tcg_ctx, cpu_tmp4, cpu_cc_srcT);
gen_exts(tcg_ctx, size, cpu_tmp4);
t0 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, true);
cc = ccprepare_make(cond, cpu_tmp4,t0, 0,-1, true,false);
cc = ccprepare_make(cond, cpu_tmp4, t0, 0, -1, true, false);
break;
default:
@@ -1187,7 +1187,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
break;
case JCC_BE:
gen_compute_eflags(s);
cc = ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_Z | CC_C, false,false);
cc = ccprepare_make(TCG_COND_NE, cpu_cc_src, 0, 0, CC_Z | CC_C, false, false);
break;
case JCC_S:
cc = gen_prepare_eflags_s(s, reg);
@@ -1202,7 +1202,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
}
tcg_gen_shri_tl(tcg_ctx, reg, cpu_cc_src, 4); /* CC_O -> CC_S */
tcg_gen_xor_tl(tcg_ctx, reg, reg, cpu_cc_src);
cc = ccprepare_make(TCG_COND_NE, reg,0, 0,CC_S, false,false);
cc = ccprepare_make(TCG_COND_NE, reg, 0, 0, CC_S, false, false);
break;
default:
case JCC_LE:
@@ -1212,7 +1212,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
}
tcg_gen_shri_tl(tcg_ctx, reg, cpu_cc_src, 4); /* CC_O -> CC_S */
tcg_gen_xor_tl(tcg_ctx, reg, reg, cpu_cc_src);
cc = ccprepare_make(TCG_COND_NE, reg,0, 0,CC_S | CC_Z, false,false);
cc = ccprepare_make(TCG_COND_NE, reg, 0, 0, CC_S | CC_Z, false, false);
break;
}
break;
@@ -3016,7 +3016,7 @@ typedef void (*SSEFunc_0_eppt)(TCGContext *s, TCGv_ptr env, TCGv_ptr reg_a, TCGv
static const SSEFunc_0_epp sse_op_table1[256][4] = {
// filler: 0x00 - 0x0e
{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},
/* 3DNow! extensions */
{ SSE_DUMMY }, /* femms */
{ SSE_DUMMY }, /* pf. . . */
@@ -3030,10 +3030,10 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = {
{ gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
{ SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
{ SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
// filler: 0x18 - 0x27
{0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0},
/* pure SSE operations */
{ SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
{ SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
@@ -3043,18 +3043,18 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = {
{ SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
{ gen_helper_ucomiss, gen_helper_ucomisd },
{ gen_helper_comiss, gen_helper_comisd },
// filler: 0x30 - 0x37
{0},{0},{0},{0},{0},{0},{0},{0},
/* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
{ SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
{0}, // filler: 0x39
{ SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
// filler: 0x3b - 0x4f
{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0},
/* pure SSE operations */
{ SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
SSE_FOP(sqrt),
@@ -3109,14 +3109,14 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = {
{ NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
{ SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
{ SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
// filler: 0x80 - 0xc1
{0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0},
{0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0},
{0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0},
{0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0},
{0},{0},
SSE_FOP(cmpeq),
// filler: 0xc3
@@ -3125,13 +3125,13 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = {
/* MMX ops and their SSE extensions */
{ SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
{ SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
{ (SSEFunc_0_epp)gen_helper_shufps,
(SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */
// filler: 0xc7 - 0xcf
{0}, {0},{0},{0},{0},{0},{0},{0},{0},
/* MMX ops and their SSE extensions */
{ NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
MMX_OP2(psrlw),
@@ -3419,7 +3419,7 @@ static const struct SSEOpHelper_epp sse_op_table6[256] = {
SSE41_OP(pmulld),
SSE41_OP(phminposuw),
// filler: 0x42 - 0xda
{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},
{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},
{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},
{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},
{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},
@@ -4848,16 +4848,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if( (b >= 0x50 && b <= 0x5a) ||
(b >= 0x5c && b <= 0x5f) ||
b == 0xc2 )
{
b == 0xc2 ) {
/* Most sse scalar operations. */
if (b1 == 2) {
sz = 2;
} else if (b1 == 3) {
sz = 3;
}
}
else if( b == 0x2e || /* ucomis[sd] */
} else if( b == 0x2e || /* ucomis[sd] */
b == 0x2f ) /* comis[sd] */
{
if (b1 == 0) {
@@ -8458,7 +8456,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
case 0x110: case 0x111: case 0x112: case 0x113: case 0x114: case 0x115: case 0x116: case 0x117: //case 0x110 ... 0x117:
case 0x128: case 0x129: case 0x12a: case 0x12b: case 0x12c: case 0x12d: case 0x12e: case 0x12f: //case 0x128 ... 0x12f:
case 0x138: case 0x139: case 0x13a:
case 0x138: case 0x139: case 0x13a:
// case 0x150 ... 0x179:
case 0x150: case 0x151: case 0x152: case 0x153: case 0x154: case 0x155: case 0x156: case 0x157:
case 0x158: case 0x159: case 0x15a: case 0x15b: case 0x15c: case 0x15d: case 0x15e: case 0x15f: