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Fix BE32 usermode address XOR

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lazymio
2022-04-05 11:55:58 +02:00
parent 7e64e620d2
commit e3d0a33ab8
3 changed files with 38 additions and 8 deletions
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24
tests/unit/test_arm.c
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@@ -727,6 +727,29 @@ static void test_arm_switch_endian()
OK(uc_close(uc));
}
static void test_armeb_ldrb(void)
{
uc_engine *uc;
const char test_code[] = "\xe5\xd2\x10\x00"; // ldrb r1, [r2]
uint64_t data_address = 0x800000;
int r1 = 0x1234;
int r2 = data_address;
uc_common_setup(&uc, UC_ARCH_ARM, UC_MODE_ARM | UC_MODE_BIG_ENDIAN, test_code, sizeof(test_code) - 1, UC_CPU_ARM_1176);
OK(uc_mem_map(uc, data_address, 1024 * 1024, UC_PROT_ALL));
OK(uc_mem_write(uc, data_address, "\x66\x67\x68\x69", 4));
OK(uc_reg_write(uc, UC_ARM_REG_R2, &r2));
OK(uc_emu_start(uc, code_start, code_start + sizeof(test_code) - 1, 0, 0));
OK(uc_reg_read(uc, UC_ARM_REG_R1, &r1));
TEST_CHECK(r1 == 0x66);
OK(uc_close(uc));
}
TEST_LIST = {{"test_arm_nop", test_arm_nop},
{"test_arm_thumb_sub", test_arm_thumb_sub},
{"test_armeb_sub", test_armeb_sub},
@@ -748,4 +771,5 @@ TEST_LIST = {{"test_arm_nop", test_arm_nop},
{"test_arm_read_sctlr", test_arm_read_sctlr},
{"test_arm_be_cpsr_sctlr", test_arm_be_cpsr_sctlr},
{"test_arm_switch_endian", test_arm_switch_endian},
{"test_armeb_ldrb", test_armeb_ldrb},
{NULL, NULL}};