From d3674f84b4556c8b1c12900f6eb32c44aa470daa Mon Sep 17 00:00:00 2001 From: mio Date: Mon, 10 Mar 2025 11:31:22 +0800 Subject: [PATCH] implement m68k cr registers --- include/unicorn/m68k.h | 16 +++++ qemu/target/m68k/unicorn.c | 123 +++++++++++++++++++++++++++++++++++++ 2 files changed, 139 insertions(+) diff --git a/include/unicorn/m68k.h b/include/unicorn/m68k.h index c4a16ee8..3e2c52a4 100644 --- a/include/unicorn/m68k.h +++ b/include/unicorn/m68k.h @@ -55,6 +55,22 @@ typedef enum uc_m68k_reg { UC_M68K_REG_SR, UC_M68K_REG_PC, + UC_M68K_REG_CR_SFC, + UC_M68K_REG_CR_DFC, + UC_M68K_REG_CR_VBR, + UC_M68K_REG_CR_CACR, + UC_M68K_REG_CR_TC, + UC_M68K_REG_CR_MMUSR, + UC_M68K_REG_CR_SRP, + UC_M68K_REG_CR_USP, + UC_M68K_REG_CR_MSP, + UC_M68K_REG_CR_ISP, + UC_M68K_REG_CR_URP, + UC_M68K_REG_CR_ITT0, + UC_M68K_REG_CR_ITT1, + UC_M68K_REG_CR_DTT0, + UC_M68K_REG_CR_DTT1, + UC_M68K_REG_ENDING, // <-- mark the end of the list of registers } uc_m68k_reg; diff --git a/qemu/target/m68k/unicorn.c b/qemu/target/m68k/unicorn.c index 56d4791e..dfa32e14 100644 --- a/qemu/target/m68k/unicorn.c +++ b/qemu/target/m68k/unicorn.c @@ -74,6 +74,62 @@ uc_err reg_read(void *_env, int mode, unsigned int regid, void *value, CHECK_REG_TYPE(uint32_t); *(uint32_t *)value = env->sr; break; + case UC_M68K_REG_CR_SFC: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->sfc; + break; + case UC_M68K_REG_CR_DFC: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->dfc; + break; + case UC_M68K_REG_CR_CACR: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->cacr; + break; + case UC_M68K_REG_CR_TC: + CHECK_REG_TYPE(uint16_t); + *(uint16_t *)value = env->mmu.tcr; + break; + case UC_M68K_REG_CR_MMUSR: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->mmu.mmusr; + break; + case UC_M68K_REG_CR_SRP: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->mmu.srp; + break; + case UC_M68K_REG_CR_USP: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->sp[M68K_USP]; + break; + case UC_M68K_REG_CR_MSP: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->sp[M68K_SSP]; + break; + case UC_M68K_REG_CR_ISP: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->sp[M68K_ISP]; + break; + case UC_M68K_REG_CR_URP: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->mmu.urp; + break; + case UC_M68K_REG_CR_ITT0: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->mmu.ttr[M68K_ITTR0]; + break; + case UC_M68K_REG_CR_ITT1: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->mmu.ttr[M68K_ITTR1]; + break; + case UC_M68K_REG_CR_DTT0: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->mmu.ttr[M68K_DTTR0]; + break; + case UC_M68K_REG_CR_DTT1: + CHECK_REG_TYPE(uint32_t); + *(uint32_t *)value = env->mmu.ttr[M68K_DTTR1]; + break; } } @@ -107,6 +163,73 @@ uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value, CHECK_REG_TYPE(uint32_t); cpu_m68k_set_sr(env, *(uint32_t *)value); break; + case UC_M68K_REG_CR_SFC: + CHECK_REG_TYPE(uint32_t); + env->sfc = (*(uint32_t *)value) & 7; + break; + case UC_M68K_REG_CR_DFC: + CHECK_REG_TYPE(uint32_t); + env->dfc = (*(uint32_t *)value) & 7; + break; + case UC_M68K_REG_CR_CACR: { + CHECK_REG_TYPE(uint32_t); + uint32_t val = *(uint32_t*)value; + if (m68k_feature(env, M68K_FEATURE_M68020)) { + env->cacr = val & 0x0000000f; + } else if (m68k_feature(env, M68K_FEATURE_M68030)) { + env->cacr = val & 0x00003f1f; + } else if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->cacr = val & 0x80008000; + } else if (m68k_feature(env, M68K_FEATURE_M68060)) { + env->cacr = val & 0xf8e0e000; + } + m68k_switch_sp(env); + break; + } + case UC_M68K_REG_CR_TC: + CHECK_REG_TYPE(uint16_t); + env->mmu.tcr = *(uint16_t *)value; + break; + case UC_M68K_REG_CR_MMUSR: + CHECK_REG_TYPE(uint32_t); + env->mmu.mmusr = *(uint32_t *)value; + break; + case UC_M68K_REG_CR_SRP: + CHECK_REG_TYPE(uint32_t); + env->mmu.srp = *(uint32_t *)value; + break; + case UC_M68K_REG_CR_USP: + CHECK_REG_TYPE(uint32_t); + env->sp[M68K_USP] = *(uint32_t *)value; + break; + case UC_M68K_REG_CR_MSP: + CHECK_REG_TYPE(uint32_t); + env->sp[M68K_SSP] = *(uint32_t *)value; + break; + case UC_M68K_REG_CR_ISP: + CHECK_REG_TYPE(uint32_t); + env->sp[M68K_ISP] = *(uint32_t *)value; + break; + case UC_M68K_REG_CR_URP: + CHECK_REG_TYPE(uint32_t); + env->mmu.urp = *(uint32_t *)value; + break; + case UC_M68K_REG_CR_ITT0: + CHECK_REG_TYPE(uint32_t); + env->mmu.ttr[M68K_ITTR0] = *(uint32_t *)value; + break; + case UC_M68K_REG_CR_ITT1: + CHECK_REG_TYPE(uint32_t); + env->mmu.ttr[M68K_ITTR1] = *(uint32_t *)value; + break; + case UC_M68K_REG_CR_DTT0: + CHECK_REG_TYPE(uint32_t); + env->mmu.ttr[M68K_DTTR0] = *(uint32_t *)value; + break; + case UC_M68K_REG_CR_DTT1: + CHECK_REG_TYPE(uint32_t); + env->mmu.ttr[M68K_DTTR1] = *(uint32_t *)value; + break; } }