TriCore Support (#1568)
* TriCore Support python sample * Update sample_tricore.py Correct attribution * Update sample_tricore.py Fixed byte code to execute properly. * Update sample_tricore.py Removed testing artifact * Added tricore msvc config-file.h * Added STATIC to tricore config and added helper methods to symbol file generation. * Update op_helper.c Use built in crc32 * Fix tricore samples and small code blocks are now handled properly * Add CPU types * Generate bindings * Format code Co-authored-by: lazymio <mio@lazym.io>
This commit is contained in:
Eric Poole
GitHub
162
qemu/target/tricore/helper.c
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162
qemu/target/tricore/helper.c
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/*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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Modified for Unicorn Engine by Eric Poole <eric.poole@aptiv.com>, 2022
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Copyright 2022 Aptiv
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "fpu/softfloat-helpers.h"
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enum {
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TLBRET_DIRTY = -4,
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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};
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#if defined(CONFIG_SOFTMMU)
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static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
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int *prot, target_ulong address,
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MMUAccessType access_type, int mmu_idx)
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{
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int ret = TLBRET_MATCH;
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*physical = address & 0xFFFFFFFF;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return ret;
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}
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hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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hwaddr phys_addr;
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int prot;
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int mmu_idx = cpu_mmu_index(&cpu->env, false);
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if (get_physical_address(&cpu->env, &phys_addr, &prot, addr,
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MMU_DATA_LOAD, mmu_idx)) {
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return -1;
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}
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return phys_addr;
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}
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#endif
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/* TODO: Add exeption support*/
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static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
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int rw, int tlb_error)
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{
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}
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bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType rw, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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hwaddr physical;
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int prot;
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int ret = 0;
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rw &= 1;
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ret = get_physical_address(env, &physical, &prot,
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address, rw, mmu_idx);
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// qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical "
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// TARGET_FMT_plx " prot %d\n",
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// __func__, (target_ulong)address, ret, physical, prot);
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if (ret == TLBRET_MATCH) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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} else {
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assert(ret < 0);
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if (probe) {
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return false;
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}
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raise_mmu_exception(env, address, rw, ret);
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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#if 0
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static void tricore_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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const char *typename;
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char *name;
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typename = object_class_get_name(oc);
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name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU));
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qemu_printf(" %s\n", name);
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g_free(name);
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}
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#endif
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#if 0
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void tricore_cpu_list(void)
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{
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GSList *list;
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list = object_class_get_list_sorted(TYPE_TRICORE_CPU, false);
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qemu_printf("Available CPUs:\n");
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g_slist_foreach(list, tricore_cpu_list_entry, NULL);
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g_slist_free(list);
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}
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#endif
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void fpu_set_state(CPUTriCoreState *env)
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{
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set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
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set_flush_inputs_to_zero(1, &env->fp_status);
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set_flush_to_zero(1, &env->fp_status);
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set_default_nan_mode(1, &env->fp_status);
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}
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uint32_t psw_read(CPUTriCoreState *env)
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{
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/* clear all USB bits */
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env->PSW &= 0x6ffffff;
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/* now set them from the cache */
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env->PSW |= ((env->PSW_USB_C != 0) << 31);
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env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1);
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env->PSW |= ((env->PSW_USB_SV & (1 << 31)) >> 2);
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env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3);
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env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4);
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return env->PSW;
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}
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void psw_write(CPUTriCoreState *env, uint32_t val)
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{
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env->PSW_USB_C = (val & MASK_USB_C);
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env->PSW_USB_V = (val & MASK_USB_V) << 1;
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env->PSW_USB_SV = (val & MASK_USB_SV) << 2;
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env->PSW_USB_AV = (val & MASK_USB_AV) << 3;
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env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4;
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env->PSW = val;
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fpu_set_state(env);
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}
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