TriCore Support (#1568)

* TriCore Support

python sample

* Update sample_tricore.py

Correct attribution

* Update sample_tricore.py

Fixed byte code to execute properly.

* Update sample_tricore.py

Removed testing artifact

* Added tricore msvc config-file.h

* Added STATIC to tricore config and added helper methods to symbol file generation.

* Update op_helper.c

Use built in crc32

* Fix tricore samples and small code blocks are now handled properly

* Add CPU types

* Generate bindings

* Format code

Co-authored-by: lazymio <mio@lazym.io>

bindings/python/sample_tricore.py

@@ -0,0 +1,57 @@
+#!/usr/bin/env python
+
+'''
+   Created for Unicorn Engine by Eric Poole <eric.poole@aptiv.com>, 2022
+   Copyright 2022 Aptiv 
+'''
+
+from __future__ import print_function
+from unicorn import *
+from unicorn.tricore_const import *
+
+# code to be emulated
+TRICORE_CODE   = b"\x82\x11\xbb\x00\x00\x08" # mov d0, #0x1; mov.u d0, #0x8000
+# memory address where emulation starts
+ADDRESS    = 0x10000
+
+# callback for tracing basic blocks
+def hook_block(uc, address, size, user_data):
+    print(">>> Tracing basic block at 0x%x, block size = 0x%x" %(address, size))
+
+# callback for tracing instructions
+def hook_code(uc, address, size, user_data):
+    print(">>> Tracing instruction at 0x%x, instruction size = 0x%x" %(address, size))
+
+# Test TriCore
+def test_tricore():
+    print("Emulate TriCore code")
+    try:
+        # Initialize emulator in TriCore mode
+        mu = Uc(UC_ARCH_TRICORE, UC_MODE_LITTLE_ENDIAN)
+
+        # map 2MB memory for this emulation
+        mu.mem_map(ADDRESS, 2 * 1024 * 1024)
+
+        # write machine code to be emulated to memory
+        mu.mem_write(ADDRESS, TRICORE_CODE)
+
+        # tracing all basic blocks with customized callback
+        mu.hook_add(UC_HOOK_BLOCK, hook_block)
+
+        # tracing one instruction at ADDRESS with customized callback
+        mu.hook_add(UC_HOOK_CODE, hook_code)
+
+        # emulate machine code in infinite time
+        mu.emu_start(ADDRESS, ADDRESS + len(TRICORE_CODE))
+
+        # now print out some registers
+        print(">>> Emulation done. Below is the CPU context")
+
+        r0 = mu.reg_read(UC_TRICORE_REG_D0)
+        print(">>> D0 = 0x%x" %r0)
+
+    except UcError as e:
+        print("ERROR: %s" % e)
+
+if __name__ == '__main__':
+    test_tricore()

bindings/python/unicorn/tricore_const.py

@@ -0,0 +1,124 @@
+# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [tricore_const.py]
+
+# TRICORE CPU
+
+UC_CPU_TRICORE_TC1796 = 0
+UC_CPU_TRICORE_TC1797 = 1
+UC_CPU_TRICORE_TC27X = 2
+UC_CPU_TRICORE_ENDING = 3
+
+# TRICORE registers
+
+UC_TRICORE_REG_INVALID = 0
+UC_TRICORE_REG_A0 = 1
+UC_TRICORE_REG_A1 = 2
+UC_TRICORE_REG_A2 = 3
+UC_TRICORE_REG_A3 = 4
+UC_TRICORE_REG_A4 = 5
+UC_TRICORE_REG_A5 = 6
+UC_TRICORE_REG_A6 = 7
+UC_TRICORE_REG_A7 = 8
+UC_TRICORE_REG_A8 = 9
+UC_TRICORE_REG_A9 = 10
+UC_TRICORE_REG_A10 = 11
+UC_TRICORE_REG_A11 = 12
+UC_TRICORE_REG_A12 = 13
+UC_TRICORE_REG_A13 = 14
+UC_TRICORE_REG_A14 = 15
+UC_TRICORE_REG_A15 = 16
+UC_TRICORE_REG_D0 = 17
+UC_TRICORE_REG_D1 = 18
+UC_TRICORE_REG_D2 = 19
+UC_TRICORE_REG_D3 = 20
+UC_TRICORE_REG_D4 = 21
+UC_TRICORE_REG_D5 = 22
+UC_TRICORE_REG_D6 = 23
+UC_TRICORE_REG_D7 = 24
+UC_TRICORE_REG_D8 = 25
+UC_TRICORE_REG_D9 = 26
+UC_TRICORE_REG_D10 = 27
+UC_TRICORE_REG_D11 = 28
+UC_TRICORE_REG_D12 = 29
+UC_TRICORE_REG_D13 = 30
+UC_TRICORE_REG_D14 = 31
+UC_TRICORE_REG_D15 = 32
+UC_TRICORE_REG_PCXI = 33
+UC_TRICORE_REG_PSW = 34
+UC_TRICORE_REG_PSW_USB_C = 35
+UC_TRICORE_REG_PSW_USB_V = 36
+UC_TRICORE_REG_PSW_USB_SV = 37
+UC_TRICORE_REG_PSW_USB_AV = 38
+UC_TRICORE_REG_PSW_USB_SAV = 39
+UC_TRICORE_REG_PC = 40
+UC_TRICORE_REG_SYSCON = 41
+UC_TRICORE_REG_CPU_ID = 42
+UC_TRICORE_REG_BIV = 43
+UC_TRICORE_REG_BTV = 44
+UC_TRICORE_REG_ISP = 45
+UC_TRICORE_REG_ICR = 46
+UC_TRICORE_REG_FCX = 47
+UC_TRICORE_REG_LCX = 48
+UC_TRICORE_REG_COMPAT = 49
+UC_TRICORE_REG_DPR0_U = 50
+UC_TRICORE_REG_DPR1_U = 51
+UC_TRICORE_REG_DPR2_U = 52
+UC_TRICORE_REG_DPR3_U = 53
+UC_TRICORE_REG_DPR0_L = 54
+UC_TRICORE_REG_DPR1_L = 55
+UC_TRICORE_REG_DPR2_L = 56
+UC_TRICORE_REG_DPR3_L = 57
+UC_TRICORE_REG_CPR0_U = 58
+UC_TRICORE_REG_CPR1_U = 59
+UC_TRICORE_REG_CPR2_U = 60
+UC_TRICORE_REG_CPR3_U = 61
+UC_TRICORE_REG_CPR0_L = 62
+UC_TRICORE_REG_CPR1_L = 63
+UC_TRICORE_REG_CPR2_L = 64
+UC_TRICORE_REG_CPR3_L = 65
+UC_TRICORE_REG_DPM0 = 66
+UC_TRICORE_REG_DPM1 = 67
+UC_TRICORE_REG_DPM2 = 68
+UC_TRICORE_REG_DPM3 = 69
+UC_TRICORE_REG_CPM0 = 70
+UC_TRICORE_REG_CPM1 = 71
+UC_TRICORE_REG_CPM2 = 72
+UC_TRICORE_REG_CPM3 = 73
+UC_TRICORE_REG_MMU_CON = 74
+UC_TRICORE_REG_MMU_ASI = 75
+UC_TRICORE_REG_MMU_TVA = 76
+UC_TRICORE_REG_MMU_TPA = 77
+UC_TRICORE_REG_MMU_TPX = 78
+UC_TRICORE_REG_MMU_TFA = 79
+UC_TRICORE_REG_BMACON = 80
+UC_TRICORE_REG_SMACON = 81
+UC_TRICORE_REG_DIEAR = 82
+UC_TRICORE_REG_DIETR = 83
+UC_TRICORE_REG_CCDIER = 84
+UC_TRICORE_REG_MIECON = 85
+UC_TRICORE_REG_PIEAR = 86
+UC_TRICORE_REG_PIETR = 87
+UC_TRICORE_REG_CCPIER = 88
+UC_TRICORE_REG_DBGSR = 89
+UC_TRICORE_REG_EXEVT = 90
+UC_TRICORE_REG_CREVT = 91
+UC_TRICORE_REG_SWEVT = 92
+UC_TRICORE_REG_TR0EVT = 93
+UC_TRICORE_REG_TR1EVT = 94
+UC_TRICORE_REG_DMS = 95
+UC_TRICORE_REG_DCX = 96
+UC_TRICORE_REG_DBGTCR = 97
+UC_TRICORE_REG_CCTRL = 98
+UC_TRICORE_REG_CCNT = 99
+UC_TRICORE_REG_ICNT = 100
+UC_TRICORE_REG_M1CNT = 101
+UC_TRICORE_REG_M2CNT = 102
+UC_TRICORE_REG_M3CNT = 103
+UC_TRICORE_REG_ENDING = 104
+UC_TRICORE_REG_GA0 = 1
+UC_TRICORE_REG_GA1 = 2
+UC_TRICORE_REG_GA8 = 9
+UC_TRICORE_REG_GA9 = 10
+UC_TRICORE_REG_SP = 11
+UC_TRICORE_REG_LR = 12
+UC_TRICORE_REG_IA = 16
+UC_TRICORE_REG_ID = 32

bindings/python/unicorn/unicorn_const.py

@@ -22,7 +22,8 @@ UC_ARCH_SPARC = 6
 UC_ARCH_M68K = 7
 UC_ARCH_RISCV = 8
 UC_ARCH_S390X = 9
-UC_ARCH_MAX = 10
+UC_ARCH_TRICORE = 10
+UC_ARCH_MAX = 11
 
 UC_MODE_LITTLE_ENDIAN = 0
 UC_MODE_BIG_ENDIAN = 1073741824