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TriCore Support (#1568)

Browse Source 
* TriCore Support

python sample

* Update sample_tricore.py

Correct attribution

* Update sample_tricore.py

Fixed byte code to execute properly.

* Update sample_tricore.py

Removed testing artifact

* Added tricore msvc config-file.h

* Added STATIC to tricore config and added helper methods to symbol file generation.

* Update op_helper.c

Use built in crc32

* Fix tricore samples and small code blocks are now handled properly

* Add CPU types

* Generate bindings

* Format code

Co-authored-by: lazymio <mio@lazym.io>
This commit is contained in:
Eric Poole
2022-04-29 17:11:34 -04:00
committed by GitHub
parent f49f62ecef
commit cfee2139a0
42 changed files with 18103 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
bindings/const_generator.py
View File

@@ -6,7 +6,7 @@ import sys, re, os
INCL_DIR = os.path.join('..', 'include', 'unicorn')
include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'sparc.h', 'm68k.h', 'ppc.h', 'riscv.h', 's390x.h', 'unicorn.h' ]
include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'sparc.h', 'm68k.h', 'ppc.h', 'riscv.h', 's390x.h', 'tricore.h', 'unicorn.h' ]
template = {
'python': {
@@ -24,6 +24,7 @@ template = {
'ppc.h': 'ppc',
'riscv.h': 'riscv',
's390x.h' : 's390x',
'tricore.h' : 'tricore',
'unicorn.h': 'unicorn',
'comment_open': '#',
'comment_close': '',
@@ -43,6 +44,7 @@ template = {
'ppc.h': 'ppc',
'riscv.h': 'riscv',
's390x.h' : 's390x',
'tricore.h' : 'tricore',
'unicorn.h': 'unicorn',
'comment_open': '#',
'comment_close': '',
@@ -62,6 +64,7 @@ template = {
'ppc.h': 'ppc',
'riscv.h': 'riscv',
's390x.h' : 's390x',
'tricore.h' : 'tricore',
'unicorn.h': 'unicorn',
'comment_open': '//',
'comment_close': '',
@@ -81,6 +84,7 @@ template = {
'ppc.h': 'Ppc',
'riscv.h': 'Riscv',
's390x.h' : 'S390x',
'tricore.h' : 'TriCore',
'unicorn.h': 'Unicorn',
'comment_open': '//',
'comment_close': '',
@@ -100,6 +104,7 @@ template = {
'ppc.h': 'Ppc',
'riscv.h': 'Riscv',
's390x.h' : 'S390x',
'tricore.h' : 'TriCore',
'unicorn.h': 'Common',
'comment_open': ' //',
'comment_close': '',
@@ -119,6 +124,7 @@ template = {
'ppc.h': 'Ppc',
'riscv.h': 'Riscv',
's390x.h' : 'S390x',
'tricore.h' : 'TriCore',
'unicorn.h': 'Unicorn',
'comment_open': '//',
'comment_close': '',

3
bindings/dotnet/UnicornManaged/Const/Common.fs
View File

@@ -29,7 +29,8 @@ module Common =
let UC_ARCH_M68K = 7
let UC_ARCH_RISCV = 8
let UC_ARCH_S390X = 9
let UC_ARCH_MAX = 10
let UC_ARCH_TRICORE = 10
let UC_ARCH_MAX = 11
let UC_MODE_LITTLE_ENDIAN = 0
let UC_MODE_BIG_ENDIAN = 1073741824

132
bindings/dotnet/UnicornManaged/Const/TriCore.fs Normal file
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@@ -0,0 +1,132 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornManaged.Const
open System
[<AutoOpen>]
module TriCore =
// TRICORE CPU
let UC_CPU_TRICORE_TC1796 = 0
let UC_CPU_TRICORE_TC1797 = 1
let UC_CPU_TRICORE_TC27X = 2
let UC_CPU_TRICORE_ENDING = 3
// TRICORE registers
let UC_TRICORE_REG_INVALID = 0
let UC_TRICORE_REG_A0 = 1
let UC_TRICORE_REG_A1 = 2
let UC_TRICORE_REG_A2 = 3
let UC_TRICORE_REG_A3 = 4
let UC_TRICORE_REG_A4 = 5
let UC_TRICORE_REG_A5 = 6
let UC_TRICORE_REG_A6 = 7
let UC_TRICORE_REG_A7 = 8
let UC_TRICORE_REG_A8 = 9
let UC_TRICORE_REG_A9 = 10
let UC_TRICORE_REG_A10 = 11
let UC_TRICORE_REG_A11 = 12
let UC_TRICORE_REG_A12 = 13
let UC_TRICORE_REG_A13 = 14
let UC_TRICORE_REG_A14 = 15
let UC_TRICORE_REG_A15 = 16
let UC_TRICORE_REG_D0 = 17
let UC_TRICORE_REG_D1 = 18
let UC_TRICORE_REG_D2 = 19
let UC_TRICORE_REG_D3 = 20
let UC_TRICORE_REG_D4 = 21
let UC_TRICORE_REG_D5 = 22
let UC_TRICORE_REG_D6 = 23
let UC_TRICORE_REG_D7 = 24
let UC_TRICORE_REG_D8 = 25
let UC_TRICORE_REG_D9 = 26
let UC_TRICORE_REG_D10 = 27
let UC_TRICORE_REG_D11 = 28
let UC_TRICORE_REG_D12 = 29
let UC_TRICORE_REG_D13 = 30
let UC_TRICORE_REG_D14 = 31
let UC_TRICORE_REG_D15 = 32
let UC_TRICORE_REG_PCXI = 33
let UC_TRICORE_REG_PSW = 34
let UC_TRICORE_REG_PSW_USB_C = 35
let UC_TRICORE_REG_PSW_USB_V = 36
let UC_TRICORE_REG_PSW_USB_SV = 37
let UC_TRICORE_REG_PSW_USB_AV = 38
let UC_TRICORE_REG_PSW_USB_SAV = 39
let UC_TRICORE_REG_PC = 40
let UC_TRICORE_REG_SYSCON = 41
let UC_TRICORE_REG_CPU_ID = 42
let UC_TRICORE_REG_BIV = 43
let UC_TRICORE_REG_BTV = 44
let UC_TRICORE_REG_ISP = 45
let UC_TRICORE_REG_ICR = 46
let UC_TRICORE_REG_FCX = 47
let UC_TRICORE_REG_LCX = 48
let UC_TRICORE_REG_COMPAT = 49
let UC_TRICORE_REG_DPR0_U = 50
let UC_TRICORE_REG_DPR1_U = 51
let UC_TRICORE_REG_DPR2_U = 52
let UC_TRICORE_REG_DPR3_U = 53
let UC_TRICORE_REG_DPR0_L = 54
let UC_TRICORE_REG_DPR1_L = 55
let UC_TRICORE_REG_DPR2_L = 56
let UC_TRICORE_REG_DPR3_L = 57
let UC_TRICORE_REG_CPR0_U = 58
let UC_TRICORE_REG_CPR1_U = 59
let UC_TRICORE_REG_CPR2_U = 60
let UC_TRICORE_REG_CPR3_U = 61
let UC_TRICORE_REG_CPR0_L = 62
let UC_TRICORE_REG_CPR1_L = 63
let UC_TRICORE_REG_CPR2_L = 64
let UC_TRICORE_REG_CPR3_L = 65
let UC_TRICORE_REG_DPM0 = 66
let UC_TRICORE_REG_DPM1 = 67
let UC_TRICORE_REG_DPM2 = 68
let UC_TRICORE_REG_DPM3 = 69
let UC_TRICORE_REG_CPM0 = 70
let UC_TRICORE_REG_CPM1 = 71
let UC_TRICORE_REG_CPM2 = 72
let UC_TRICORE_REG_CPM3 = 73
let UC_TRICORE_REG_MMU_CON = 74
let UC_TRICORE_REG_MMU_ASI = 75
let UC_TRICORE_REG_MMU_TVA = 76
let UC_TRICORE_REG_MMU_TPA = 77
let UC_TRICORE_REG_MMU_TPX = 78
let UC_TRICORE_REG_MMU_TFA = 79
let UC_TRICORE_REG_BMACON = 80
let UC_TRICORE_REG_SMACON = 81
let UC_TRICORE_REG_DIEAR = 82
let UC_TRICORE_REG_DIETR = 83
let UC_TRICORE_REG_CCDIER = 84
let UC_TRICORE_REG_MIECON = 85
let UC_TRICORE_REG_PIEAR = 86
let UC_TRICORE_REG_PIETR = 87
let UC_TRICORE_REG_CCPIER = 88
let UC_TRICORE_REG_DBGSR = 89
let UC_TRICORE_REG_EXEVT = 90
let UC_TRICORE_REG_CREVT = 91
let UC_TRICORE_REG_SWEVT = 92
let UC_TRICORE_REG_TR0EVT = 93
let UC_TRICORE_REG_TR1EVT = 94
let UC_TRICORE_REG_DMS = 95
let UC_TRICORE_REG_DCX = 96
let UC_TRICORE_REG_DBGTCR = 97
let UC_TRICORE_REG_CCTRL = 98
let UC_TRICORE_REG_CCNT = 99
let UC_TRICORE_REG_ICNT = 100
let UC_TRICORE_REG_M1CNT = 101
let UC_TRICORE_REG_M2CNT = 102
let UC_TRICORE_REG_M3CNT = 103
let UC_TRICORE_REG_ENDING = 104
let UC_TRICORE_REG_GA0 = 1
let UC_TRICORE_REG_GA1 = 2
let UC_TRICORE_REG_GA8 = 9
let UC_TRICORE_REG_GA9 = 10
let UC_TRICORE_REG_SP = 11
let UC_TRICORE_REG_LR = 12
let UC_TRICORE_REG_IA = 16
let UC_TRICORE_REG_ID = 32

127
bindings/go/unicorn/tricore_const.go Normal file
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@@ -0,0 +1,127 @@
package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [tricore_const.go]
const (
// TRICORE CPU
CPU_TRICORE_TC1796 = 0
CPU_TRICORE_TC1797 = 1
CPU_TRICORE_TC27X = 2
CPU_TRICORE_ENDING = 3
// TRICORE registers
TRICORE_REG_INVALID = 0
TRICORE_REG_A0 = 1
TRICORE_REG_A1 = 2
TRICORE_REG_A2 = 3
TRICORE_REG_A3 = 4
TRICORE_REG_A4 = 5
TRICORE_REG_A5 = 6
TRICORE_REG_A6 = 7
TRICORE_REG_A7 = 8
TRICORE_REG_A8 = 9
TRICORE_REG_A9 = 10
TRICORE_REG_A10 = 11
TRICORE_REG_A11 = 12
TRICORE_REG_A12 = 13
TRICORE_REG_A13 = 14
TRICORE_REG_A14 = 15
TRICORE_REG_A15 = 16
TRICORE_REG_D0 = 17
TRICORE_REG_D1 = 18
TRICORE_REG_D2 = 19
TRICORE_REG_D3 = 20
TRICORE_REG_D4 = 21
TRICORE_REG_D5 = 22
TRICORE_REG_D6 = 23
TRICORE_REG_D7 = 24
TRICORE_REG_D8 = 25
TRICORE_REG_D9 = 26
TRICORE_REG_D10 = 27
TRICORE_REG_D11 = 28
TRICORE_REG_D12 = 29
TRICORE_REG_D13 = 30
TRICORE_REG_D14 = 31
TRICORE_REG_D15 = 32
TRICORE_REG_PCXI = 33
TRICORE_REG_PSW = 34
TRICORE_REG_PSW_USB_C = 35
TRICORE_REG_PSW_USB_V = 36
TRICORE_REG_PSW_USB_SV = 37
TRICORE_REG_PSW_USB_AV = 38
TRICORE_REG_PSW_USB_SAV = 39
TRICORE_REG_PC = 40
TRICORE_REG_SYSCON = 41
TRICORE_REG_CPU_ID = 42
TRICORE_REG_BIV = 43
TRICORE_REG_BTV = 44
TRICORE_REG_ISP = 45
TRICORE_REG_ICR = 46
TRICORE_REG_FCX = 47
TRICORE_REG_LCX = 48
TRICORE_REG_COMPAT = 49
TRICORE_REG_DPR0_U = 50
TRICORE_REG_DPR1_U = 51
TRICORE_REG_DPR2_U = 52
TRICORE_REG_DPR3_U = 53
TRICORE_REG_DPR0_L = 54
TRICORE_REG_DPR1_L = 55
TRICORE_REG_DPR2_L = 56
TRICORE_REG_DPR3_L = 57
TRICORE_REG_CPR0_U = 58
TRICORE_REG_CPR1_U = 59
TRICORE_REG_CPR2_U = 60
TRICORE_REG_CPR3_U = 61
TRICORE_REG_CPR0_L = 62
TRICORE_REG_CPR1_L = 63
TRICORE_REG_CPR2_L = 64
TRICORE_REG_CPR3_L = 65
TRICORE_REG_DPM0 = 66
TRICORE_REG_DPM1 = 67
TRICORE_REG_DPM2 = 68
TRICORE_REG_DPM3 = 69
TRICORE_REG_CPM0 = 70
TRICORE_REG_CPM1 = 71
TRICORE_REG_CPM2 = 72
TRICORE_REG_CPM3 = 73
TRICORE_REG_MMU_CON = 74
TRICORE_REG_MMU_ASI = 75
TRICORE_REG_MMU_TVA = 76
TRICORE_REG_MMU_TPA = 77
TRICORE_REG_MMU_TPX = 78
TRICORE_REG_MMU_TFA = 79
TRICORE_REG_BMACON = 80
TRICORE_REG_SMACON = 81
TRICORE_REG_DIEAR = 82
TRICORE_REG_DIETR = 83
TRICORE_REG_CCDIER = 84
TRICORE_REG_MIECON = 85
TRICORE_REG_PIEAR = 86
TRICORE_REG_PIETR = 87
TRICORE_REG_CCPIER = 88
TRICORE_REG_DBGSR = 89
TRICORE_REG_EXEVT = 90
TRICORE_REG_CREVT = 91
TRICORE_REG_SWEVT = 92
TRICORE_REG_TR0EVT = 93
TRICORE_REG_TR1EVT = 94
TRICORE_REG_DMS = 95
TRICORE_REG_DCX = 96
TRICORE_REG_DBGTCR = 97
TRICORE_REG_CCTRL = 98
TRICORE_REG_CCNT = 99
TRICORE_REG_ICNT = 100
TRICORE_REG_M1CNT = 101
TRICORE_REG_M2CNT = 102
TRICORE_REG_M3CNT = 103
TRICORE_REG_ENDING = 104
TRICORE_REG_GA0 = 1
TRICORE_REG_GA1 = 2
TRICORE_REG_GA8 = 9
TRICORE_REG_GA9 = 10
TRICORE_REG_SP = 11
TRICORE_REG_LR = 12
TRICORE_REG_IA = 16
TRICORE_REG_ID = 32
)

3
bindings/go/unicorn/unicorn_const.go
View File

@@ -24,7 +24,8 @@ const (
ARCH_M68K = 7
ARCH_RISCV = 8
ARCH_S390X = 9
ARCH_MAX = 10
ARCH_TRICORE = 10
ARCH_MAX = 11
MODE_LITTLE_ENDIAN = 0
MODE_BIG_ENDIAN = 1073741824

130
bindings/java/unicorn/TriCoreConst.java Normal file
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@@ -0,0 +1,130 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
package unicorn;
public interface TriCoreConst {
// TRICORE CPU
public static final int UC_CPU_TRICORE_TC1796 = 0;
public static final int UC_CPU_TRICORE_TC1797 = 1;
public static final int UC_CPU_TRICORE_TC27X = 2;
public static final int UC_CPU_TRICORE_ENDING = 3;
// TRICORE registers
public static final int UC_TRICORE_REG_INVALID = 0;
public static final int UC_TRICORE_REG_A0 = 1;
public static final int UC_TRICORE_REG_A1 = 2;
public static final int UC_TRICORE_REG_A2 = 3;
public static final int UC_TRICORE_REG_A3 = 4;
public static final int UC_TRICORE_REG_A4 = 5;
public static final int UC_TRICORE_REG_A5 = 6;
public static final int UC_TRICORE_REG_A6 = 7;
public static final int UC_TRICORE_REG_A7 = 8;
public static final int UC_TRICORE_REG_A8 = 9;
public static final int UC_TRICORE_REG_A9 = 10;
public static final int UC_TRICORE_REG_A10 = 11;
public static final int UC_TRICORE_REG_A11 = 12;
public static final int UC_TRICORE_REG_A12 = 13;
public static final int UC_TRICORE_REG_A13 = 14;
public static final int UC_TRICORE_REG_A14 = 15;
public static final int UC_TRICORE_REG_A15 = 16;
public static final int UC_TRICORE_REG_D0 = 17;
public static final int UC_TRICORE_REG_D1 = 18;
public static final int UC_TRICORE_REG_D2 = 19;
public static final int UC_TRICORE_REG_D3 = 20;
public static final int UC_TRICORE_REG_D4 = 21;
public static final int UC_TRICORE_REG_D5 = 22;
public static final int UC_TRICORE_REG_D6 = 23;
public static final int UC_TRICORE_REG_D7 = 24;
public static final int UC_TRICORE_REG_D8 = 25;
public static final int UC_TRICORE_REG_D9 = 26;
public static final int UC_TRICORE_REG_D10 = 27;
public static final int UC_TRICORE_REG_D11 = 28;
public static final int UC_TRICORE_REG_D12 = 29;
public static final int UC_TRICORE_REG_D13 = 30;
public static final int UC_TRICORE_REG_D14 = 31;
public static final int UC_TRICORE_REG_D15 = 32;
public static final int UC_TRICORE_REG_PCXI = 33;
public static final int UC_TRICORE_REG_PSW = 34;
public static final int UC_TRICORE_REG_PSW_USB_C = 35;
public static final int UC_TRICORE_REG_PSW_USB_V = 36;
public static final int UC_TRICORE_REG_PSW_USB_SV = 37;
public static final int UC_TRICORE_REG_PSW_USB_AV = 38;
public static final int UC_TRICORE_REG_PSW_USB_SAV = 39;
public static final int UC_TRICORE_REG_PC = 40;
public static final int UC_TRICORE_REG_SYSCON = 41;
public static final int UC_TRICORE_REG_CPU_ID = 42;
public static final int UC_TRICORE_REG_BIV = 43;
public static final int UC_TRICORE_REG_BTV = 44;
public static final int UC_TRICORE_REG_ISP = 45;
public static final int UC_TRICORE_REG_ICR = 46;
public static final int UC_TRICORE_REG_FCX = 47;
public static final int UC_TRICORE_REG_LCX = 48;
public static final int UC_TRICORE_REG_COMPAT = 49;
public static final int UC_TRICORE_REG_DPR0_U = 50;
public static final int UC_TRICORE_REG_DPR1_U = 51;
public static final int UC_TRICORE_REG_DPR2_U = 52;
public static final int UC_TRICORE_REG_DPR3_U = 53;
public static final int UC_TRICORE_REG_DPR0_L = 54;
public static final int UC_TRICORE_REG_DPR1_L = 55;
public static final int UC_TRICORE_REG_DPR2_L = 56;
public static final int UC_TRICORE_REG_DPR3_L = 57;
public static final int UC_TRICORE_REG_CPR0_U = 58;
public static final int UC_TRICORE_REG_CPR1_U = 59;
public static final int UC_TRICORE_REG_CPR2_U = 60;
public static final int UC_TRICORE_REG_CPR3_U = 61;
public static final int UC_TRICORE_REG_CPR0_L = 62;
public static final int UC_TRICORE_REG_CPR1_L = 63;
public static final int UC_TRICORE_REG_CPR2_L = 64;
public static final int UC_TRICORE_REG_CPR3_L = 65;
public static final int UC_TRICORE_REG_DPM0 = 66;
public static final int UC_TRICORE_REG_DPM1 = 67;
public static final int UC_TRICORE_REG_DPM2 = 68;
public static final int UC_TRICORE_REG_DPM3 = 69;
public static final int UC_TRICORE_REG_CPM0 = 70;
public static final int UC_TRICORE_REG_CPM1 = 71;
public static final int UC_TRICORE_REG_CPM2 = 72;
public static final int UC_TRICORE_REG_CPM3 = 73;
public static final int UC_TRICORE_REG_MMU_CON = 74;
public static final int UC_TRICORE_REG_MMU_ASI = 75;
public static final int UC_TRICORE_REG_MMU_TVA = 76;
public static final int UC_TRICORE_REG_MMU_TPA = 77;
public static final int UC_TRICORE_REG_MMU_TPX = 78;
public static final int UC_TRICORE_REG_MMU_TFA = 79;
public static final int UC_TRICORE_REG_BMACON = 80;
public static final int UC_TRICORE_REG_SMACON = 81;
public static final int UC_TRICORE_REG_DIEAR = 82;
public static final int UC_TRICORE_REG_DIETR = 83;
public static final int UC_TRICORE_REG_CCDIER = 84;
public static final int UC_TRICORE_REG_MIECON = 85;
public static final int UC_TRICORE_REG_PIEAR = 86;
public static final int UC_TRICORE_REG_PIETR = 87;
public static final int UC_TRICORE_REG_CCPIER = 88;
public static final int UC_TRICORE_REG_DBGSR = 89;
public static final int UC_TRICORE_REG_EXEVT = 90;
public static final int UC_TRICORE_REG_CREVT = 91;
public static final int UC_TRICORE_REG_SWEVT = 92;
public static final int UC_TRICORE_REG_TR0EVT = 93;
public static final int UC_TRICORE_REG_TR1EVT = 94;
public static final int UC_TRICORE_REG_DMS = 95;
public static final int UC_TRICORE_REG_DCX = 96;
public static final int UC_TRICORE_REG_DBGTCR = 97;
public static final int UC_TRICORE_REG_CCTRL = 98;
public static final int UC_TRICORE_REG_CCNT = 99;
public static final int UC_TRICORE_REG_ICNT = 100;
public static final int UC_TRICORE_REG_M1CNT = 101;
public static final int UC_TRICORE_REG_M2CNT = 102;
public static final int UC_TRICORE_REG_M3CNT = 103;
public static final int UC_TRICORE_REG_ENDING = 104;
public static final int UC_TRICORE_REG_GA0 = 1;
public static final int UC_TRICORE_REG_GA1 = 2;
public static final int UC_TRICORE_REG_GA8 = 9;
public static final int UC_TRICORE_REG_GA9 = 10;
public static final int UC_TRICORE_REG_SP = 11;
public static final int UC_TRICORE_REG_LR = 12;
public static final int UC_TRICORE_REG_IA = 16;
public static final int UC_TRICORE_REG_ID = 32;
}

3
bindings/java/unicorn/UnicornConst.java
View File

@@ -26,7 +26,8 @@ public interface UnicornConst {
public static final int UC_ARCH_M68K = 7;
public static final int UC_ARCH_RISCV = 8;
public static final int UC_ARCH_S390X = 9;
public static final int UC_ARCH_MAX = 10;
public static final int UC_ARCH_TRICORE = 10;
public static final int UC_ARCH_MAX = 11;
public static final int UC_MODE_LITTLE_ENDIAN = 0;
public static final int UC_MODE_BIG_ENDIAN = 1073741824;

132
bindings/pascal/unicorn/TriCoreConst.pas Normal file
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@@ -0,0 +1,132 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
unit TriCoreConst;
interface
const
// TRICORE CPU
UC_CPU_TRICORE_TC1796 = 0;
UC_CPU_TRICORE_TC1797 = 1;
UC_CPU_TRICORE_TC27X = 2;
UC_CPU_TRICORE_ENDING = 3;
// TRICORE registers
UC_TRICORE_REG_INVALID = 0;
UC_TRICORE_REG_A0 = 1;
UC_TRICORE_REG_A1 = 2;
UC_TRICORE_REG_A2 = 3;
UC_TRICORE_REG_A3 = 4;
UC_TRICORE_REG_A4 = 5;
UC_TRICORE_REG_A5 = 6;
UC_TRICORE_REG_A6 = 7;
UC_TRICORE_REG_A7 = 8;
UC_TRICORE_REG_A8 = 9;
UC_TRICORE_REG_A9 = 10;
UC_TRICORE_REG_A10 = 11;
UC_TRICORE_REG_A11 = 12;
UC_TRICORE_REG_A12 = 13;
UC_TRICORE_REG_A13 = 14;
UC_TRICORE_REG_A14 = 15;
UC_TRICORE_REG_A15 = 16;
UC_TRICORE_REG_D0 = 17;
UC_TRICORE_REG_D1 = 18;
UC_TRICORE_REG_D2 = 19;
UC_TRICORE_REG_D3 = 20;
UC_TRICORE_REG_D4 = 21;
UC_TRICORE_REG_D5 = 22;
UC_TRICORE_REG_D6 = 23;
UC_TRICORE_REG_D7 = 24;
UC_TRICORE_REG_D8 = 25;
UC_TRICORE_REG_D9 = 26;
UC_TRICORE_REG_D10 = 27;
UC_TRICORE_REG_D11 = 28;
UC_TRICORE_REG_D12 = 29;
UC_TRICORE_REG_D13 = 30;
UC_TRICORE_REG_D14 = 31;
UC_TRICORE_REG_D15 = 32;
UC_TRICORE_REG_PCXI = 33;
UC_TRICORE_REG_PSW = 34;
UC_TRICORE_REG_PSW_USB_C = 35;
UC_TRICORE_REG_PSW_USB_V = 36;
UC_TRICORE_REG_PSW_USB_SV = 37;
UC_TRICORE_REG_PSW_USB_AV = 38;
UC_TRICORE_REG_PSW_USB_SAV = 39;
UC_TRICORE_REG_PC = 40;
UC_TRICORE_REG_SYSCON = 41;
UC_TRICORE_REG_CPU_ID = 42;
UC_TRICORE_REG_BIV = 43;
UC_TRICORE_REG_BTV = 44;
UC_TRICORE_REG_ISP = 45;
UC_TRICORE_REG_ICR = 46;
UC_TRICORE_REG_FCX = 47;
UC_TRICORE_REG_LCX = 48;
UC_TRICORE_REG_COMPAT = 49;
UC_TRICORE_REG_DPR0_U = 50;
UC_TRICORE_REG_DPR1_U = 51;
UC_TRICORE_REG_DPR2_U = 52;
UC_TRICORE_REG_DPR3_U = 53;
UC_TRICORE_REG_DPR0_L = 54;
UC_TRICORE_REG_DPR1_L = 55;
UC_TRICORE_REG_DPR2_L = 56;
UC_TRICORE_REG_DPR3_L = 57;
UC_TRICORE_REG_CPR0_U = 58;
UC_TRICORE_REG_CPR1_U = 59;
UC_TRICORE_REG_CPR2_U = 60;
UC_TRICORE_REG_CPR3_U = 61;
UC_TRICORE_REG_CPR0_L = 62;
UC_TRICORE_REG_CPR1_L = 63;
UC_TRICORE_REG_CPR2_L = 64;
UC_TRICORE_REG_CPR3_L = 65;
UC_TRICORE_REG_DPM0 = 66;
UC_TRICORE_REG_DPM1 = 67;
UC_TRICORE_REG_DPM2 = 68;
UC_TRICORE_REG_DPM3 = 69;
UC_TRICORE_REG_CPM0 = 70;
UC_TRICORE_REG_CPM1 = 71;
UC_TRICORE_REG_CPM2 = 72;
UC_TRICORE_REG_CPM3 = 73;
UC_TRICORE_REG_MMU_CON = 74;
UC_TRICORE_REG_MMU_ASI = 75;
UC_TRICORE_REG_MMU_TVA = 76;
UC_TRICORE_REG_MMU_TPA = 77;
UC_TRICORE_REG_MMU_TPX = 78;
UC_TRICORE_REG_MMU_TFA = 79;
UC_TRICORE_REG_BMACON = 80;
UC_TRICORE_REG_SMACON = 81;
UC_TRICORE_REG_DIEAR = 82;
UC_TRICORE_REG_DIETR = 83;
UC_TRICORE_REG_CCDIER = 84;
UC_TRICORE_REG_MIECON = 85;
UC_TRICORE_REG_PIEAR = 86;
UC_TRICORE_REG_PIETR = 87;
UC_TRICORE_REG_CCPIER = 88;
UC_TRICORE_REG_DBGSR = 89;
UC_TRICORE_REG_EXEVT = 90;
UC_TRICORE_REG_CREVT = 91;
UC_TRICORE_REG_SWEVT = 92;
UC_TRICORE_REG_TR0EVT = 93;
UC_TRICORE_REG_TR1EVT = 94;
UC_TRICORE_REG_DMS = 95;
UC_TRICORE_REG_DCX = 96;
UC_TRICORE_REG_DBGTCR = 97;
UC_TRICORE_REG_CCTRL = 98;
UC_TRICORE_REG_CCNT = 99;
UC_TRICORE_REG_ICNT = 100;
UC_TRICORE_REG_M1CNT = 101;
UC_TRICORE_REG_M2CNT = 102;
UC_TRICORE_REG_M3CNT = 103;
UC_TRICORE_REG_ENDING = 104;
UC_TRICORE_REG_GA0 = 1;
UC_TRICORE_REG_GA1 = 2;
UC_TRICORE_REG_GA8 = 9;
UC_TRICORE_REG_GA9 = 10;
UC_TRICORE_REG_SP = 11;
UC_TRICORE_REG_LR = 12;
UC_TRICORE_REG_IA = 16;
UC_TRICORE_REG_ID = 32;
implementation
end.

3
bindings/pascal/unicorn/UnicornConst.pas
View File

@@ -27,7 +27,8 @@ const UC_API_MAJOR = 2;
UC_ARCH_M68K = 7;
UC_ARCH_RISCV = 8;
UC_ARCH_S390X = 9;
UC_ARCH_MAX = 10;
UC_ARCH_TRICORE = 10;
UC_ARCH_MAX = 11;
UC_MODE_LITTLE_ENDIAN = 0;
UC_MODE_BIG_ENDIAN = 1073741824;

57
bindings/python/sample_tricore.py Executable file
View File

@@ -0,0 +1,57 @@
#!/usr/bin/env python
'''
Created for Unicorn Engine by Eric Poole <eric.poole@aptiv.com>, 2022
Copyright 2022 Aptiv
'''
from __future__ import print_function
from unicorn import *
from unicorn.tricore_const import *
# code to be emulated
TRICORE_CODE = b"\x82\x11\xbb\x00\x00\x08" # mov d0, #0x1; mov.u d0, #0x8000
# memory address where emulation starts
ADDRESS = 0x10000
# callback for tracing basic blocks
def hook_block(uc, address, size, user_data):
print(">>> Tracing basic block at 0x%x, block size = 0x%x" %(address, size))
# callback for tracing instructions
def hook_code(uc, address, size, user_data):
print(">>> Tracing instruction at 0x%x, instruction size = 0x%x" %(address, size))
# Test TriCore
def test_tricore():
print("Emulate TriCore code")
try:
# Initialize emulator in TriCore mode
mu = Uc(UC_ARCH_TRICORE, UC_MODE_LITTLE_ENDIAN)
# map 2MB memory for this emulation
mu.mem_map(ADDRESS, 2 * 1024 * 1024)
# write machine code to be emulated to memory
mu.mem_write(ADDRESS, TRICORE_CODE)
# tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block)
# tracing one instruction at ADDRESS with customized callback
mu.hook_add(UC_HOOK_CODE, hook_code)
# emulate machine code in infinite time
mu.emu_start(ADDRESS, ADDRESS + len(TRICORE_CODE))
# now print out some registers
print(">>> Emulation done. Below is the CPU context")
r0 = mu.reg_read(UC_TRICORE_REG_D0)
print(">>> D0 = 0x%x" %r0)
except UcError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_tricore()

124
bindings/python/unicorn/tricore_const.py Normal file
View File

@@ -0,0 +1,124 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [tricore_const.py]
# TRICORE CPU
UC_CPU_TRICORE_TC1796 = 0
UC_CPU_TRICORE_TC1797 = 1
UC_CPU_TRICORE_TC27X = 2
UC_CPU_TRICORE_ENDING = 3
# TRICORE registers
UC_TRICORE_REG_INVALID = 0
UC_TRICORE_REG_A0 = 1
UC_TRICORE_REG_A1 = 2
UC_TRICORE_REG_A2 = 3
UC_TRICORE_REG_A3 = 4
UC_TRICORE_REG_A4 = 5
UC_TRICORE_REG_A5 = 6
UC_TRICORE_REG_A6 = 7
UC_TRICORE_REG_A7 = 8
UC_TRICORE_REG_A8 = 9
UC_TRICORE_REG_A9 = 10
UC_TRICORE_REG_A10 = 11
UC_TRICORE_REG_A11 = 12
UC_TRICORE_REG_A12 = 13
UC_TRICORE_REG_A13 = 14
UC_TRICORE_REG_A14 = 15
UC_TRICORE_REG_A15 = 16
UC_TRICORE_REG_D0 = 17
UC_TRICORE_REG_D1 = 18
UC_TRICORE_REG_D2 = 19
UC_TRICORE_REG_D3 = 20
UC_TRICORE_REG_D4 = 21
UC_TRICORE_REG_D5 = 22
UC_TRICORE_REG_D6 = 23
UC_TRICORE_REG_D7 = 24
UC_TRICORE_REG_D8 = 25
UC_TRICORE_REG_D9 = 26
UC_TRICORE_REG_D10 = 27
UC_TRICORE_REG_D11 = 28
UC_TRICORE_REG_D12 = 29
UC_TRICORE_REG_D13 = 30
UC_TRICORE_REG_D14 = 31
UC_TRICORE_REG_D15 = 32
UC_TRICORE_REG_PCXI = 33
UC_TRICORE_REG_PSW = 34
UC_TRICORE_REG_PSW_USB_C = 35
UC_TRICORE_REG_PSW_USB_V = 36
UC_TRICORE_REG_PSW_USB_SV = 37
UC_TRICORE_REG_PSW_USB_AV = 38
UC_TRICORE_REG_PSW_USB_SAV = 39
UC_TRICORE_REG_PC = 40
UC_TRICORE_REG_SYSCON = 41
UC_TRICORE_REG_CPU_ID = 42
UC_TRICORE_REG_BIV = 43
UC_TRICORE_REG_BTV = 44
UC_TRICORE_REG_ISP = 45
UC_TRICORE_REG_ICR = 46
UC_TRICORE_REG_FCX = 47
UC_TRICORE_REG_LCX = 48
UC_TRICORE_REG_COMPAT = 49
UC_TRICORE_REG_DPR0_U = 50
UC_TRICORE_REG_DPR1_U = 51
UC_TRICORE_REG_DPR2_U = 52
UC_TRICORE_REG_DPR3_U = 53
UC_TRICORE_REG_DPR0_L = 54
UC_TRICORE_REG_DPR1_L = 55
UC_TRICORE_REG_DPR2_L = 56
UC_TRICORE_REG_DPR3_L = 57
UC_TRICORE_REG_CPR0_U = 58
UC_TRICORE_REG_CPR1_U = 59
UC_TRICORE_REG_CPR2_U = 60
UC_TRICORE_REG_CPR3_U = 61
UC_TRICORE_REG_CPR0_L = 62
UC_TRICORE_REG_CPR1_L = 63
UC_TRICORE_REG_CPR2_L = 64
UC_TRICORE_REG_CPR3_L = 65
UC_TRICORE_REG_DPM0 = 66
UC_TRICORE_REG_DPM1 = 67
UC_TRICORE_REG_DPM2 = 68
UC_TRICORE_REG_DPM3 = 69
UC_TRICORE_REG_CPM0 = 70
UC_TRICORE_REG_CPM1 = 71
UC_TRICORE_REG_CPM2 = 72
UC_TRICORE_REG_CPM3 = 73
UC_TRICORE_REG_MMU_CON = 74
UC_TRICORE_REG_MMU_ASI = 75
UC_TRICORE_REG_MMU_TVA = 76
UC_TRICORE_REG_MMU_TPA = 77
UC_TRICORE_REG_MMU_TPX = 78
UC_TRICORE_REG_MMU_TFA = 79
UC_TRICORE_REG_BMACON = 80
UC_TRICORE_REG_SMACON = 81
UC_TRICORE_REG_DIEAR = 82
UC_TRICORE_REG_DIETR = 83
UC_TRICORE_REG_CCDIER = 84
UC_TRICORE_REG_MIECON = 85
UC_TRICORE_REG_PIEAR = 86
UC_TRICORE_REG_PIETR = 87
UC_TRICORE_REG_CCPIER = 88
UC_TRICORE_REG_DBGSR = 89
UC_TRICORE_REG_EXEVT = 90
UC_TRICORE_REG_CREVT = 91
UC_TRICORE_REG_SWEVT = 92
UC_TRICORE_REG_TR0EVT = 93
UC_TRICORE_REG_TR1EVT = 94
UC_TRICORE_REG_DMS = 95
UC_TRICORE_REG_DCX = 96
UC_TRICORE_REG_DBGTCR = 97
UC_TRICORE_REG_CCTRL = 98
UC_TRICORE_REG_CCNT = 99
UC_TRICORE_REG_ICNT = 100
UC_TRICORE_REG_M1CNT = 101
UC_TRICORE_REG_M2CNT = 102
UC_TRICORE_REG_M3CNT = 103
UC_TRICORE_REG_ENDING = 104
UC_TRICORE_REG_GA0 = 1
UC_TRICORE_REG_GA1 = 2
UC_TRICORE_REG_GA8 = 9
UC_TRICORE_REG_GA9 = 10
UC_TRICORE_REG_SP = 11
UC_TRICORE_REG_LR = 12
UC_TRICORE_REG_IA = 16
UC_TRICORE_REG_ID = 32

3
bindings/python/unicorn/unicorn_const.py
View File

@@ -22,7 +22,8 @@ UC_ARCH_SPARC = 6
UC_ARCH_M68K = 7
UC_ARCH_RISCV = 8
UC_ARCH_S390X = 9
UC_ARCH_MAX = 10
UC_ARCH_TRICORE = 10
UC_ARCH_MAX = 11
UC_MODE_LITTLE_ENDIAN = 0
UC_MODE_BIG_ENDIAN = 1073741824

127
bindings/ruby/unicorn_gem/lib/unicorn_engine/tricore_const.rb Normal file
View File

@@ -0,0 +1,127 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [tricore_const.rb]
module UnicornEngine
# TRICORE CPU
UC_CPU_TRICORE_TC1796 = 0
UC_CPU_TRICORE_TC1797 = 1
UC_CPU_TRICORE_TC27X = 2
UC_CPU_TRICORE_ENDING = 3
# TRICORE registers
UC_TRICORE_REG_INVALID = 0
UC_TRICORE_REG_A0 = 1
UC_TRICORE_REG_A1 = 2
UC_TRICORE_REG_A2 = 3
UC_TRICORE_REG_A3 = 4
UC_TRICORE_REG_A4 = 5
UC_TRICORE_REG_A5 = 6
UC_TRICORE_REG_A6 = 7
UC_TRICORE_REG_A7 = 8
UC_TRICORE_REG_A8 = 9
UC_TRICORE_REG_A9 = 10
UC_TRICORE_REG_A10 = 11
UC_TRICORE_REG_A11 = 12
UC_TRICORE_REG_A12 = 13
UC_TRICORE_REG_A13 = 14
UC_TRICORE_REG_A14 = 15
UC_TRICORE_REG_A15 = 16
UC_TRICORE_REG_D0 = 17
UC_TRICORE_REG_D1 = 18
UC_TRICORE_REG_D2 = 19
UC_TRICORE_REG_D3 = 20
UC_TRICORE_REG_D4 = 21
UC_TRICORE_REG_D5 = 22
UC_TRICORE_REG_D6 = 23
UC_TRICORE_REG_D7 = 24
UC_TRICORE_REG_D8 = 25
UC_TRICORE_REG_D9 = 26
UC_TRICORE_REG_D10 = 27
UC_TRICORE_REG_D11 = 28
UC_TRICORE_REG_D12 = 29
UC_TRICORE_REG_D13 = 30
UC_TRICORE_REG_D14 = 31
UC_TRICORE_REG_D15 = 32
UC_TRICORE_REG_PCXI = 33
UC_TRICORE_REG_PSW = 34
UC_TRICORE_REG_PSW_USB_C = 35
UC_TRICORE_REG_PSW_USB_V = 36
UC_TRICORE_REG_PSW_USB_SV = 37
UC_TRICORE_REG_PSW_USB_AV = 38
UC_TRICORE_REG_PSW_USB_SAV = 39
UC_TRICORE_REG_PC = 40
UC_TRICORE_REG_SYSCON = 41
UC_TRICORE_REG_CPU_ID = 42
UC_TRICORE_REG_BIV = 43
UC_TRICORE_REG_BTV = 44
UC_TRICORE_REG_ISP = 45
UC_TRICORE_REG_ICR = 46
UC_TRICORE_REG_FCX = 47
UC_TRICORE_REG_LCX = 48
UC_TRICORE_REG_COMPAT = 49
UC_TRICORE_REG_DPR0_U = 50
UC_TRICORE_REG_DPR1_U = 51
UC_TRICORE_REG_DPR2_U = 52
UC_TRICORE_REG_DPR3_U = 53
UC_TRICORE_REG_DPR0_L = 54
UC_TRICORE_REG_DPR1_L = 55
UC_TRICORE_REG_DPR2_L = 56
UC_TRICORE_REG_DPR3_L = 57
UC_TRICORE_REG_CPR0_U = 58
UC_TRICORE_REG_CPR1_U = 59
UC_TRICORE_REG_CPR2_U = 60
UC_TRICORE_REG_CPR3_U = 61
UC_TRICORE_REG_CPR0_L = 62
UC_TRICORE_REG_CPR1_L = 63
UC_TRICORE_REG_CPR2_L = 64
UC_TRICORE_REG_CPR3_L = 65
UC_TRICORE_REG_DPM0 = 66
UC_TRICORE_REG_DPM1 = 67
UC_TRICORE_REG_DPM2 = 68
UC_TRICORE_REG_DPM3 = 69
UC_TRICORE_REG_CPM0 = 70
UC_TRICORE_REG_CPM1 = 71
UC_TRICORE_REG_CPM2 = 72
UC_TRICORE_REG_CPM3 = 73
UC_TRICORE_REG_MMU_CON = 74
UC_TRICORE_REG_MMU_ASI = 75
UC_TRICORE_REG_MMU_TVA = 76
UC_TRICORE_REG_MMU_TPA = 77
UC_TRICORE_REG_MMU_TPX = 78
UC_TRICORE_REG_MMU_TFA = 79
UC_TRICORE_REG_BMACON = 80
UC_TRICORE_REG_SMACON = 81
UC_TRICORE_REG_DIEAR = 82
UC_TRICORE_REG_DIETR = 83
UC_TRICORE_REG_CCDIER = 84
UC_TRICORE_REG_MIECON = 85
UC_TRICORE_REG_PIEAR = 86
UC_TRICORE_REG_PIETR = 87
UC_TRICORE_REG_CCPIER = 88
UC_TRICORE_REG_DBGSR = 89
UC_TRICORE_REG_EXEVT = 90
UC_TRICORE_REG_CREVT = 91
UC_TRICORE_REG_SWEVT = 92
UC_TRICORE_REG_TR0EVT = 93
UC_TRICORE_REG_TR1EVT = 94
UC_TRICORE_REG_DMS = 95
UC_TRICORE_REG_DCX = 96
UC_TRICORE_REG_DBGTCR = 97
UC_TRICORE_REG_CCTRL = 98
UC_TRICORE_REG_CCNT = 99
UC_TRICORE_REG_ICNT = 100
UC_TRICORE_REG_M1CNT = 101
UC_TRICORE_REG_M2CNT = 102
UC_TRICORE_REG_M3CNT = 103
UC_TRICORE_REG_ENDING = 104
UC_TRICORE_REG_GA0 = 1
UC_TRICORE_REG_GA1 = 2
UC_TRICORE_REG_GA8 = 9
UC_TRICORE_REG_GA9 = 10
UC_TRICORE_REG_SP = 11
UC_TRICORE_REG_LR = 12
UC_TRICORE_REG_IA = 16
UC_TRICORE_REG_ID = 32
end

3
bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb
View File

@@ -24,7 +24,8 @@ module UnicornEngine
UC_ARCH_M68K = 7
UC_ARCH_RISCV = 8
UC_ARCH_S390X = 9
UC_ARCH_MAX = 10
UC_ARCH_TRICORE = 10
UC_ARCH_MAX = 11
UC_MODE_LITTLE_ENDIAN = 0
UC_MODE_BIG_ENDIAN = 1073741824