Squashed commit of the following:

commit 520c6647c32f02d83083d969d416154aa95e922c
Merge: 6bb29b12 b999f507
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:14:23 2025 +0800

    merge dev

commit 6bb29b12f1d9f452365cc9cb5bc2d65ef376af30
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:13:12 2025 +0800

    enable test

commit bcb8b363ef12ac295cf4fe4f1645416e5f0ea6ae
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:13:06 2025 +0800

    also logging

commit 5972fc156b7379d09582c745d6d597e07555f2f4
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:12:58 2025 +0800

    no unlimited translation

commit 7d600feebf9055505918e50d0af8b529a3eba542
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:12:47 2025 +0800

    Ignore bindings.rs

commit dde4d50f2c7713156ac3bc284287480e4d92005f
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sun Apr 6 03:26:22 2025 -0400

    alias `uc_mips_reg` to `UC_MIPS_REG`

commit 04234ae01ba7c82d9717eaae64cdda289ce3b832
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sun Apr 6 01:13:00 2025 -0400

    remove bindings.rs

commit edec1300cd7c2d8ef4babbd51f6bcba2e126bdd7
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Apr 5 14:29:40 2025 -0400

    address review

commit feb157b28b6c262c5dc3d810ec54de55a25bcd6e
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 22:40:53 2025 -0400

    ci(rust): rework workflow

    The notable changes are migrating to
    `actions-rust-lang/setup-rust-toolchain` for setting up Rust as it's
    maintained, and using `katyo/publish-crates` for publishing crates in a
    workspace

commit c1c7a8f8ed841b6ec5b4abe57013a1c2c9748c60
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 22:40:06 2025 -0400

    build(rust): set `rust-version` to 1.85

commit 8df938c9f8b478160213707674157103b0893caf
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 21:53:21 2025 -0400

    fix(rust): correct unsound pointer cast

    The size of `T` is not guaranteed to be the size of `i32` - all we know
    is that `T` is `Into<i32>`, so we should first copy them over into an
    `i32` array

commit 3059b2583a60aa0cac9278afc945ed87f7ddb65e
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 20:13:26 2025 -0400

    docs(rust): update readme

commit 7db69a888e58a4bda20083e4e0771d26a327ad13
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:58:30 2025 -0400

    feat(rust): add comprehensive tests

    These tests are copied over from the C tests

commit 78f2207f0e0481aef4de6d5908f8dc699a39a8d5
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:57:27 2025 -0400

    feat(rust): add tcg hook

commit 46e53328531ec3279dadbf18c16b493432227b31
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:56:55 2025 -0400

    feat(rust): add a hook for arm64 sys instructions

commit d1b58ee8282bf1eeeefbf68c87c2cf7c50c90320
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:56:35 2025 -0400

    feat(rust): add the ability to read the arm coprocessor register

commit d304da18b9e6741042b2a70657437be8f39f5c7c
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:55:29 2025 -0400

    feat(rust): add missing `Context` methods

commit 0dd87833081ac9db1feaf5bae8c839a7a2ae4947
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:44:51 2025 -0400

    refactor(rust): remove unnecessary code

    `unicorn-engine-sys` will provide the necessary constants & types

commit da3d2fa7c3ecd3ae8fdb6672b6c5ea23da4570ff
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:43:57 2025 -0400

    feat(rust): add a workspace `Cargo.toml`, and use `unicorn-engine-sys`

commit b27a2a93e4ac43aa2079e936df4dd30a1f8f329a
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:38:06 2025 -0400

    feat(rust): introduce `unicorn-engine-sys` crate

    This crate contains generated Rust bindings to the C library via
    bindgen. It is independent from the main `unicorn-engine` bindings,
    which will leverage this

commit bcec87a3f6e316e328683c303ccfa89e530a6c56
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:31:24 2025 -0400

    test(m68k): actually assert an expectation

    This test did not actually test for anything before

commit bc7e65ca96164496eb2e250b1f296a33a8aa58ee
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:31:09 2025 -0400

    style(test): use bitflag shorthands

commit 0ab4b7fefb3ca17b0b5977d7b204291c5de184ad
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:22:13 2025 -0400

    fix(mips): lowercase enum name `uc_mips_reg`

    This aligns with other architectures

Co-authored-by: Amaan Qureshi <amaanq12@gmail.com>

bindings/rust/sys/src/lib.rs

@@ -0,0 +1,342 @@
+#![allow(non_camel_case_types)]
+
+mod bindings;
+pub use bindings::*;
+
+impl uc_error {
+    /// Calls `op` if the result is Ok, otherwise returns the [`Err`] value of `self`.
+    pub fn and_then<U, F: FnOnce() -> Result<U, Self>>(self, op: F) -> Result<U, Self> {
+        if self == Self::OK { op() } else { Err(self) }
+    }
+
+    /// Returns `res` if the result is Ok, otherwise returns the [`Err`] value of `self`.
+    /// Arguments passed to this are eagerly evaluated; if you are passing the result
+    /// of a function call, it is recommended to use [`uc_error::and_then`] instead, as it's lazily
+    /// evaluated.
+    pub fn and<U>(self, res: Result<U, Self>) -> Result<U, Self> {
+        if self == Self::OK { res } else { Err(self) }
+    }
+}
+
+impl From<uc_error> for Result<(), uc_error> {
+    fn from(value: uc_error) -> Self {
+        if value == uc_error::OK {
+            Ok(())
+        } else {
+            Err(value)
+        }
+    }
+}
+
+impl TryFrom<usize> for Arch {
+    type Error = uc_error;
+
+    fn try_from(v: usize) -> Result<Self, Self::Error> {
+        match v {
+            x if x == Self::ARM as usize => Ok(Self::ARM),
+            x if x == Self::ARM64 as usize => Ok(Self::ARM64),
+            x if x == Self::MIPS as usize => Ok(Self::MIPS),
+            x if x == Self::X86 as usize => Ok(Self::X86),
+            x if x == Self::PPC as usize => Ok(Self::PPC),
+            x if x == Self::SPARC as usize => Ok(Self::SPARC),
+            x if x == Self::M68K as usize => Ok(Self::M68K),
+            x if x == Self::RISCV as usize => Ok(Self::RISCV),
+            x if x == Self::S390X as usize => Ok(Self::S390X),
+            x if x == Self::TRICORE as usize => Ok(Self::TRICORE),
+            x if x == Self::MAX as usize => Ok(Self::MAX),
+            _ => Err(uc_error::ARCH),
+        }
+    }
+}
+
+impl TryFrom<i32> for Mode {
+    type Error = uc_error;
+
+    #[allow(clippy::cognitive_complexity)]
+    fn try_from(v: i32) -> Result<Self, Self::Error> {
+        match v {
+            x if x == Self::LITTLE_ENDIAN.0 as i32 => Ok(Self::LITTLE_ENDIAN),
+            x if x == Self::BIG_ENDIAN.0 as i32 => Ok(Self::BIG_ENDIAN),
+            x if x == Self::ARM.0 as i32 => Ok(Self::ARM),
+            x if x == Self::THUMB.0 as i32 => Ok(Self::THUMB),
+            x if x == Self::MCLASS.0 as i32 => Ok(Self::MCLASS),
+            x if x == Self::V8.0 as i32 => Ok(Self::V8),
+            x if x == Self::ARMBE8.0 as i32 => Ok(Self::ARMBE8),
+            x if x == Self::ARM926.0 as i32 => Ok(Self::ARM926),
+            x if x == Self::ARM946.0 as i32 => Ok(Self::ARM946),
+            x if x == Self::ARM1176.0 as i32 => Ok(Self::ARM1176),
+            x if x == Self::MICRO.0 as i32 => Ok(Self::MICRO),
+            x if x == Self::MIPS3.0 as i32 => Ok(Self::MIPS3),
+            x if x == Self::MIPS32R6.0 as i32 => Ok(Self::MIPS32R6),
+            x if x == Self::MIPS32.0 as i32 => Ok(Self::MIPS32),
+            x if x == Self::MIPS64.0 as i32 => Ok(Self::MIPS64),
+            x if x == Self::MODE_16.0 as i32 => Ok(Self::MODE_16),
+            x if x == Self::MODE_32.0 as i32 => Ok(Self::MODE_32),
+            x if x == Self::MODE_64.0 as i32 => Ok(Self::MODE_64),
+            x if x == Self::PPC32.0 as i32 => Ok(Self::PPC32),
+            x if x == Self::PPC64.0 as i32 => Ok(Self::PPC64),
+            x if x == Self::QPX.0 as i32 => Ok(Self::QPX),
+            x if x == Self::SPARC32.0 as i32 => Ok(Self::SPARC32),
+            x if x == Self::SPARC64.0 as i32 => Ok(Self::SPARC64),
+            x if x == Self::V9.0 as i32 => Ok(Self::V9),
+            x if x == Self::RISCV32.0 as i32 => Ok(Self::RISCV32),
+            x if x == Self::RISCV64.0 as i32 => Ok(Self::RISCV64),
+            _ => Err(uc_error::MODE),
+        }
+    }
+}
+
+impl HookType {
+    pub const MEM_UNMAPPED: Self =
+        Self(Self::MEM_READ_UNMAPPED.0 | Self::MEM_WRITE_UNMAPPED.0 | Self::MEM_FETCH_UNMAPPED.0);
+
+    pub const MEM_PROT: Self =
+        Self(Self::MEM_READ_PROT.0 | Self::MEM_WRITE_PROT.0 | Self::MEM_FETCH_PROT.0);
+
+    pub const MEM_VALID: Self = Self(Self::MEM_READ.0 | Self::MEM_WRITE.0 | Self::MEM_FETCH.0);
+
+    pub const MEM_READ_INVALID: Self = Self(Self::MEM_READ_UNMAPPED.0 | Self::MEM_READ_PROT.0);
+
+    pub const MEM_WRITE_INVALID: Self = Self(Self::MEM_WRITE_UNMAPPED.0 | Self::MEM_WRITE_PROT.0);
+
+    pub const MEM_FETCH_INVALID: Self = Self(Self::MEM_FETCH_UNMAPPED.0 | Self::MEM_FETCH_PROT.0);
+
+    pub const MEM_INVALID: Self =
+        Self(Self::MEM_READ_INVALID.0 | Self::MEM_WRITE_INVALID.0 | Self::MEM_FETCH_INVALID.0);
+
+    pub const MEM_ALL: Self = Self(Self::MEM_VALID.0 | Self::MEM_INVALID.0);
+}
+
+impl ControlType {
+    pub const IO_READ: Self = Self(1 << 31);
+
+    pub const IO_WRITE: Self = Self(1 << 30);
+}
+
+impl From<M68kCpuModel> for i32 {
+    fn from(value: M68kCpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&M68kCpuModel> for i32 {
+    fn from(value: &M68kCpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<X86CpuModel> for i32 {
+    fn from(value: X86CpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&X86CpuModel> for i32 {
+    fn from(value: &X86CpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<ArmCpuModel> for i32 {
+    fn from(value: ArmCpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&ArmCpuModel> for i32 {
+    fn from(value: &ArmCpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<Arm64CpuModel> for i32 {
+    fn from(value: Arm64CpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&Arm64CpuModel> for i32 {
+    fn from(value: &Arm64CpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<Mips32CpuModel> for i32 {
+    fn from(value: Mips32CpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&Mips32CpuModel> for i32 {
+    fn from(value: &Mips32CpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<Mips64CpuModel> for i32 {
+    fn from(value: Mips64CpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&Mips64CpuModel> for i32 {
+    fn from(value: &Mips64CpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<Sparc32CpuModel> for i32 {
+    fn from(value: Sparc32CpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&Sparc32CpuModel> for i32 {
+    fn from(value: &Sparc32CpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<Sparc64CpuModel> for i32 {
+    fn from(value: Sparc64CpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&Sparc64CpuModel> for i32 {
+    fn from(value: &Sparc64CpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<PpcCpuModel> for i32 {
+    fn from(value: PpcCpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&PpcCpuModel> for i32 {
+    fn from(value: &PpcCpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<Ppc64CpuModel> for i32 {
+    fn from(value: Ppc64CpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&Ppc64CpuModel> for i32 {
+    fn from(value: &Ppc64CpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<Riscv32CpuModel> for i32 {
+    fn from(value: Riscv32CpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&Riscv32CpuModel> for i32 {
+    fn from(value: &Riscv32CpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<Riscv64CpuModel> for i32 {
+    fn from(value: Riscv64CpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&Riscv64CpuModel> for i32 {
+    fn from(value: &Riscv64CpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<S390xCpuModel> for i32 {
+    fn from(value: S390xCpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&S390xCpuModel> for i32 {
+    fn from(value: &S390xCpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<TricoreCpuModel> for i32 {
+    fn from(value: TricoreCpuModel) -> Self {
+        value as Self
+    }
+}
+
+impl From<&TricoreCpuModel> for i32 {
+    fn from(value: &TricoreCpuModel) -> Self {
+        *value as Self
+    }
+}
+
+impl From<RegisterM68K> for i32 {
+    fn from(value: RegisterM68K) -> Self {
+        value as Self
+    }
+}
+
+impl From<RegisterX86> for i32 {
+    fn from(value: RegisterX86) -> Self {
+        value as Self
+    }
+}
+
+impl From<RegisterARM> for i32 {
+    fn from(value: RegisterARM) -> Self {
+        value as Self
+    }
+}
+
+impl From<RegisterARM64> for i32 {
+    fn from(value: RegisterARM64) -> Self {
+        value as Self
+    }
+}
+
+impl From<RegisterMIPS> for i32 {
+    fn from(value: RegisterMIPS) -> Self {
+        value as Self
+    }
+}
+
+impl From<RegisterSPARC> for i32 {
+    fn from(value: RegisterSPARC) -> Self {
+        value as Self
+    }
+}
+
+impl From<RegisterPPC> for i32 {
+    fn from(value: RegisterPPC) -> Self {
+        value as Self
+    }
+}
+
+impl From<RegisterRISCV> for i32 {
+    fn from(value: RegisterRISCV) -> Self {
+        value as Self
+    }
+}
+
+impl From<RegisterS390X> for i32 {
+    fn from(value: RegisterS390X) -> Self {
+        value as Self
+    }
+}
+
+impl From<RegisterTRICORE> for i32 {
+    fn from(value: RegisterTRICORE) -> Self {
+        value as Self
+    }
+}