From b4eb933ec8b9a3d80ebfda079902859be14ab920 Mon Sep 17 00:00:00 2001 From: mio Date: Tue, 11 Feb 2025 16:24:49 +0800 Subject: [PATCH] CI(full),CI(release): Do not refer to ATOMIC128 symbols if not available --- qemu/target/arm/helper-a64.c | 18 +++++++++++++++++ qemu/target/i386/mem_helper.c | 6 ++++-- qemu/target/ppc/mem_helper.c | 35 ++++++++++++++++++++++++++++++---- qemu/target/s390x/mem_helper.c | 25 ++++++++++++++++++++---- 4 files changed, 74 insertions(+), 10 deletions(-) diff --git a/qemu/target/arm/helper-a64.c b/qemu/target/arm/helper-a64.c index 8b698824..9cb4326e 100644 --- a/qemu/target/arm/helper-a64.c +++ b/qemu/target/arm/helper-a64.c @@ -568,6 +568,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { +#ifdef HAVE_CMPXCHG128 Int128 oldv, cmpv, newv; uintptr_t ra = GETPC(); bool success; @@ -585,6 +586,10 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr, success = int128_eq(oldv, cmpv); return !success; +#else + g_assert_not_reached(); + return 0; +#endif } uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, @@ -620,6 +625,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { +#ifdef HAVE_CMPXCHG128 Int128 oldv, cmpv, newv; uintptr_t ra = GETPC(); bool success; @@ -641,12 +647,17 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr, success = int128_eq(oldv, cmpv); return !success; +#else + g_assert_not_reached(); + return 0; +#endif } /* Writes back the old data into Rs. */ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { +#ifdef HAVE_CMPXCHG128 Int128 oldv, cmpv, newv; uintptr_t ra = GETPC(); int mem_idx; @@ -663,11 +674,15 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, env->xregs[rs] = int128_getlo(oldv); env->xregs[rs + 1] = int128_gethi(oldv); +#else + g_assert_not_reached(); +#endif } void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_hi, uint64_t new_lo) { +#ifdef HAVE_CMPXCHG128 Int128 oldv, cmpv, newv; uintptr_t ra = GETPC(); int mem_idx; @@ -684,6 +699,9 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, env->xregs[rs + 1] = int128_getlo(oldv); env->xregs[rs] = int128_gethi(oldv); +#else + g_assert_not_reached(); +#endif } /* diff --git a/qemu/target/i386/mem_helper.c b/qemu/target/i386/mem_helper.c index 0f3946b9..aee3c930 100644 --- a/qemu/target/i386/mem_helper.c +++ b/qemu/target/i386/mem_helper.c @@ -129,7 +129,8 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) if ((a0 & 0xf) != 0) { raise_exception_ra(env, EXCP0D_GPF, ra); - } else if (HAVE_CMPXCHG128) { + } else { +#ifdef HAVE_CMPXCHG128 int eflags = cpu_cc_compute_all(env, CC_OP); Int128 cmpv = int128_make128(env->regs[R_EAX], env->regs[R_EDX]); @@ -148,8 +149,9 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) eflags &= ~CC_Z; } CC_SRC = eflags; - } else { +#else cpu_loop_exit_atomic(env_cpu(env), ra); +#endif } } #endif diff --git a/qemu/target/ppc/mem_helper.c b/qemu/target/ppc/mem_helper.c index 6113e281..47079c62 100644 --- a/qemu/target/ppc/mem_helper.c +++ b/qemu/target/ppc/mem_helper.c @@ -374,10 +374,10 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, } #ifdef TARGET_PPC64 -#ifdef HAVE_ATOMIC128 uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, uint32_t opidx) { +#ifdef HAVE_ATOMIC128 Int128 ret; /* We will have raised EXCP_ATOMIC from the translator. */ @@ -385,11 +385,16 @@ uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); env->retxh = int128_gethi(ret); return int128_getlo(ret); +#else + g_assert_not_reached(); + return 0; +#endif } uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, uint32_t opidx) { +#ifdef HAVE_ATOMIC128 Int128 ret; /* We will have raised EXCP_ATOMIC from the translator. */ @@ -397,36 +402,51 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); env->retxh = int128_gethi(ret); return int128_getlo(ret); +#else + g_assert_not_reached(); + return 0; +#endif } void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, uint64_t lo, uint64_t hi, uint32_t opidx) { +#ifdef HAVE_ATOMIC128 Int128 val; /* We will have raised EXCP_ATOMIC from the translator. */ assert(HAVE_ATOMIC128); val = int128_make128(lo, hi); helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); +#else + g_assert_not_reached(); + return 0; +#endif } void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, uint64_t lo, uint64_t hi, uint32_t opidx) { +#ifdef HAVE_ATOMIC128 Int128 val; /* We will have raised EXCP_ATOMIC from the translator. */ assert(HAVE_ATOMIC128); val = int128_make128(lo, hi); helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); +#else + g_assert_not_reached(); + return 0; +#endif } #endif -#ifdef HAVE_CMPXCHG128 + uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, uint64_t new_lo, uint64_t new_hi, uint32_t opidx) { +#ifdef HAVE_CMPXCHG128 bool success = false; /* We will have raised EXCP_ATOMIC from the translator. */ @@ -443,12 +463,17 @@ uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, } env->reserve_addr = -1; return env->so + success * CRF_EQ_BIT; +#else + g_assert_not_reached(); + return 0; +#endif } uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, uint64_t new_lo, uint64_t new_hi, uint32_t opidx) { +#ifdef HAVE_CMPXCHG128 bool success = false; /* We will have raised EXCP_ATOMIC from the translator. */ @@ -465,9 +490,11 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, } env->reserve_addr = -1; return env->so + success * CRF_EQ_BIT; +#else + g_assert_not_reached(); + return 0; +#endif } -#endif -#endif /*****************************************************************************/ /* Altivec extension helpers */ diff --git a/qemu/target/s390x/mem_helper.c b/qemu/target/s390x/mem_helper.c index 7058ae45..20766dd7 100644 --- a/qemu/target/s390x/mem_helper.c +++ b/qemu/target/s390x/mem_helper.c @@ -1695,6 +1695,7 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, uint32_t r1, uint32_t r3) { +#ifdef HAVE_CMPXCHG128 uintptr_t ra = GETPC(); Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]); Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]); @@ -1713,6 +1714,9 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, env->cc_op = fail; env->regs[r1] = int128_gethi(oldv); env->regs[r1 + 1] = int128_getlo(oldv); +#else + g_assert_not_reached(); +#endif } static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, @@ -1829,13 +1833,15 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); - } else if (HAVE_CMPXCHG128) { + } else { +#ifdef HAVE_CMPXCHG128 TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); ov = helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); cc = !int128_eq(ov, cv); - } else { +#else /* Note that we asserted !parallel above. */ g_assert_not_reached(); +#endif } env->regs[r3 + 0] = int128_gethi(ov); @@ -1868,13 +1874,15 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, if (!parallel) { cpu_stq_data_ra(env, a2 + 0, svh, ra); cpu_stq_data_ra(env, a2 + 8, svl, ra); - } else if (HAVE_ATOMIC128) { + } else { +#ifdef HAVE_ATOMIC128 TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 sv = int128_make128(svl, svh); helper_atomic_sto_be_mmu(env, a2, sv, oi, ra); - } else { +#else /* Note that we asserted !parallel above. */ g_assert_not_reached(); +#endif } break; default: @@ -2348,6 +2356,7 @@ uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) { +#ifdef HAVE_ATOMIC128 uintptr_t ra = GETPC(); uint64_t hi, lo; int mem_idx; @@ -2364,6 +2373,10 @@ uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) env->retxl = lo; return hi; +#else + g_assert_not_reached(); + return 0; +#endif } /* store pair to quadword */ @@ -2380,6 +2393,7 @@ void HELPER(stpq)(CPUS390XState *env, uint64_t addr, void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, uint64_t low, uint64_t high) { +#ifdef HAVE_ATOMIC128 uintptr_t ra = GETPC(); int mem_idx; TCGMemOpIdx oi; @@ -2391,6 +2405,9 @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); v = int128_make128(low, high); helper_atomic_sto_be_mmu(env, addr, v, oi, ra); +#else + g_assert_not_reached(); +#endif } /* Execute instruction. This instruction executes an insn modified with