Check CPU model for uc_ctl
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@@ -29,7 +29,7 @@ static void test_arm64_until(void)
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uint64_t r_x28 = 0x12341234;
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uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1,
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UC_CPU_AARCH64_A72);
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UC_CPU_ARM64_A72);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_ARM64_REG_X16, &r_x16));
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@@ -57,7 +57,7 @@ static void test_arm64_code_patching(void)
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uc_engine *uc;
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char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1
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uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1,
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UC_CPU_AARCH64_A72);
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UC_CPU_ARM64_A72);
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// zero out x0
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uint64_t r_x0 = 0x0;
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OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0));
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@@ -87,7 +87,7 @@ static void test_arm64_code_patching_count(void)
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uc_engine *uc;
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char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1
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uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1,
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UC_CPU_AARCH64_A72);
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UC_CPU_ARM64_A72);
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// zero out x0
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uint64_t r_x0 = 0x0;
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OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0));
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@@ -120,7 +120,7 @@ static void test_arm64_v8_pac(void)
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uint64_t r_x9, r_x8, mem;
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uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1,
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UC_CPU_AARCH64_MAX);
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UC_CPU_ARM64_MAX);
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OK(uc_mem_map(uc, 0x40000, 0x1000, UC_PROT_ALL));
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OK(uc_mem_write(uc, 0x40000, "\x00\x00\x00\x00\x00\x00\x00\x00", 8));
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@@ -179,7 +179,7 @@ static void test_arm64_mrs_hook(void)
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char code[] = "\x62\xd0\x3b\xd5";
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uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_LITTLE_ENDIAN | UC_MODE_ARM,
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code, sizeof(code) - 1, UC_CPU_AARCH64_A72);
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code, sizeof(code) - 1, UC_CPU_ARM64_A72);
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OK(uc_hook_add(uc, &hk, UC_HOOK_INSN, (void *)test_arm64_mrs_hook_cb, NULL,
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1, 0, UC_ARM64_INS_MRS));
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