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import Unicorn2

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This commit is contained in:
Nguyen Anh Quynh
2021-10-03 22:14:44 +08:00
parent 772558119a
commit aaaea14214
837 changed files with 368717 additions and 200912 deletions
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4
qemu/target/riscv/README Normal file
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code under riscv32/ is from riscv32-softmmu/target/riscv/*.inc.c
code under riscv64/ is from riscv64-softmmu/target/riscv/*.inc.c
WARNING: these code are autogen from scripts/decodetree.py, DO NOT modify them.

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qemu/target/riscv/cpu-param.h Normal file
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/*
* RISC-V cpu parameters for qemu.
*
* Copyright (c) 2017-2018 SiFive, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef RISCV_CPU_PARAM_H
#define RISCV_CPU_PARAM_H 1
#if defined(TARGET_RISCV64)
# define TARGET_LONG_BITS 64
# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
#elif defined(TARGET_RISCV32)
# define TARGET_LONG_BITS 32
# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
#define NB_MMU_MODES 4
#endif

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qemu/target/riscv/cpu.c Normal file
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/*
* QEMU RISC-V CPU
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/ctype.h"
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "fpu/softfloat-helpers.h"
#include <uc_priv.h>
/* RISC-V CPU definitions */
// static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
"x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
"x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
"x28/t3", "x29/t4", "x30/t5", "x31/t6"
};
const char * const riscv_fpr_regnames[] = {
"f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
"f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
"f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
"f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
"f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
"f30/ft10", "f31/ft11"
};
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;
}
static void set_priv_version(CPURISCVState *env, int priv_ver)
{
env->priv_ver = priv_ver;
}
static void set_feature(CPURISCVState *env, int feature)
{
env->features |= (1ULL << feature);
}
static void set_resetvec(CPURISCVState *env, int resetvec)
{
env->resetvec = resetvec;
}
static void riscv_any_cpu_init(CPUState *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_11_0);
set_resetvec(env, DEFAULT_RSTVEC);
}
#if defined(TARGET_RISCV32)
// rv32
static void riscv_base32_cpu_init(CPUState *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, 0);
}
// sifive-u34
static void rv32gcsu_priv1_10_0_cpu_init(CPUState *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
}
// sifive-e31
static void rv32imacu_nommu_cpu_init(CPUState *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_PMP);
}
#elif defined(TARGET_RISCV64)
// rv64
static void riscv_base64_cpu_init(CPUState *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, 0);
}
// sifive-u54
static void rv64gcsu_priv1_10_0_cpu_init(CPUState *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
}
// sifive-e51
static void rv64imacu_nommu_cpu_init(CPUState *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_PMP);
}
#endif
static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->pc = value;
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->pc = tb->pc;
}
static bool riscv_cpu_has_work(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
/*
* Definition of the WFI instruction requires it to ignore the privilege
* mode and delegation registers, but respect individual enables
*/
return (env->mip & env->mie) != 0;
}
void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
target_ulong *data)
{
env->pc = data[0];
}
static void riscv_cpu_reset(CPUState *dev)
{
CPUState *cs = CPU(dev);
RISCVCPU *cpu = RISCV_CPU(cs);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
CPURISCVState *env = &cpu->env;
mcc->parent_reset(cs);
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
env->mcause = 0;
env->pc = env->resetvec;
cs->exception_index = EXCP_NONE;
env->load_res = -1;
set_default_nan_mode(1, &env->fp_status);
}
static void riscv_cpu_realize(struct uc_struct *uc, CPUState *dev)
{
CPUState *cs = CPU(dev);
RISCVCPU *cpu = RISCV_CPU(dev);
CPURISCVState *env = &cpu->env;
int priv_version = PRIV_VERSION_1_11_0;
target_ulong target_misa = 0;
cpu_exec_realizefn(cs);
if (cpu->cfg.priv_spec) {
if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
priv_version = PRIV_VERSION_1_11_0;
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
priv_version = PRIV_VERSION_1_10_0;
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
priv_version = PRIV_VERSION_1_09_1;
} else {
// error_setg(errp, "Unsupported privilege spec version '%s'", cpu->cfg.priv_spec);
return;
}
}
set_priv_version(env, priv_version);
set_resetvec(env, DEFAULT_RSTVEC);
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
}
if (cpu->cfg.pmp) {
set_feature(env, RISCV_FEATURE_PMP);
}
/* If misa isn't set (rv32 and rv64 machines) set it here */
if (!env->misa) {
/* Do some ISA extension error checking */
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
//error_setg(errp, "I and E extensions are incompatible");
return;
}
if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
// error_setg(errp, "Either I or E extension must be set");
return;
}
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
cpu->cfg.ext_a & cpu->cfg.ext_f & cpu->cfg.ext_d)) {
// warn_report("Setting G will also set IMAFD");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
cpu->cfg.ext_a = true;
cpu->cfg.ext_f = true;
cpu->cfg.ext_d = true;
}
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
target_misa |= RVI;
}
if (cpu->cfg.ext_e) {
target_misa |= RVE;
}
if (cpu->cfg.ext_m) {
target_misa |= RVM;
}
if (cpu->cfg.ext_a) {
target_misa |= RVA;
}
if (cpu->cfg.ext_f) {
target_misa |= RVF;
}
if (cpu->cfg.ext_d) {
target_misa |= RVD;
}
if (cpu->cfg.ext_c) {
target_misa |= RVC;
}
if (cpu->cfg.ext_s) {
target_misa |= RVS;
}
if (cpu->cfg.ext_u) {
target_misa |= RVU;
}
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
set_misa(env, RVXLEN | target_misa);
}
cpu_reset(cs);
}
static void riscv_cpu_init(struct uc_struct *uc, CPUState *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
// unicorn
env->uc = uc;
cpu_set_cpustate_pointers(cpu);
}
static void riscv_cpu_class_init(struct uc_struct *uc, CPUClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
mcc->parent_reset = cc->reset;
cc->reset = riscv_cpu_reset;
cc->has_work = riscv_cpu_has_work;
cc->do_interrupt = riscv_cpu_do_interrupt;
cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->set_pc = riscv_cpu_set_pc;
cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->tcg_initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
}
typedef struct CPUModelInfo {
const char *name;
void (*initfn)(CPUState *obj);
} CPUModelInfo;
static const CPUModelInfo cpu_models[] = {
{TYPE_RISCV_CPU_ANY, riscv_any_cpu_init},
#ifdef TARGET_RISCV32
{TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init},
{TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init},
{TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init},
#endif
#ifdef TARGET_RISCV64
{TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init},
{TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init},
{TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init},
#endif
};
RISCVCPU *cpu_riscv_init(struct uc_struct *uc, const char *cpu_model)
{
RISCVCPU *cpu;
CPUState *cs;
CPUClass *cc;
int i;
cpu = calloc(1, sizeof(*cpu));
if (cpu == NULL) {
return NULL;
}
#ifdef TARGET_RISCV32
if (!cpu_model) {
cpu_model = TYPE_RISCV_CPU_SIFIVE_U34;
}
#else
/* TARGET_RISCV64 */
if (!cpu_model) {
cpu_model = TYPE_RISCV_CPU_SIFIVE_U54;
}
#endif
cs = (CPUState *)cpu;
cc = (CPUClass *)&cpu->cc;
cs->cc = cc;
cs->uc = uc;
uc->cpu = (CPUState *)cpu;
/* init CPUClass */
cpu_class_init(uc, cc);
/* init RISCVCPUClass */
riscv_cpu_class_init(uc, cc, NULL);
/* init CPUState */
cpu_common_initfn(uc, cs);
/* init CPU */
riscv_cpu_init(uc, cs);
/* init specific CPU model */
for (i = 0; i < ARRAY_SIZE(cpu_models); i++) {
if (strcmp(cpu_model, cpu_models[i].name) == 0) {
cpu_models[i].initfn(cs);
break;
}
}
/* realize CPU */
riscv_cpu_realize(uc, cs);
// init addresss space
cpu_address_space_init(cs, 0, cs->memory);
qemu_init_vcpu(cs);
return cpu;
}

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qemu/target/riscv/cpu.h Normal file
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/*
* QEMU RISC-V CPU
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef RISCV_CPU_H
#define RISCV_CPU_H
#include "hw/core/cpu.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
typedef struct TCGContext TCGContext;
#define TYPE_RISCV_CPU "riscv-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
#if defined(TARGET_RISCV32)
#define RVXLEN RV32
#elif defined(TARGET_RISCV64)
#define RVXLEN RV64
#endif
#define RV(x) ((target_ulong)1 << (x - 'A'))
#define RVI RV('I')
#define RVE RV('E') /* E and I are mutually exclusive */
#define RVM RV('M')
#define RVA RV('A')
#define RVF RV('F')
#define RVD RV('D')
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
is currently no bit in misa to indicate whether an MMU exists or not
so a cpu features bitfield is required, likewise for optional PMP support */
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_MISA
};
#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
#define TRANSLATE_SUCCESS 0
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
struct CPURISCVState {
target_ulong gpr[32];
uint64_t fpr[32]; /* assume both F and D extensions */
target_ulong pc;
target_ulong load_res;
target_ulong load_val;
target_ulong frm;
target_ulong badaddr;
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
target_ulong misa;
target_ulong misa_mask;
uint32_t features;
target_ulong priv;
/* This contains QEMU specific information about the virt state. */
target_ulong virt;
target_ulong resetvec;
target_ulong mhartid;
target_ulong mstatus;
target_ulong mip;
#ifdef TARGET_RISCV32
target_ulong mstatush;
#endif
uint32_t miclaim;
target_ulong mie;
target_ulong mideleg;
target_ulong sptbr; /* until: priv-1.9.1 */
target_ulong satp; /* since: priv-1.10.0 */
target_ulong sbadaddr;
target_ulong mbadaddr;
target_ulong medeleg;
target_ulong stvec;
target_ulong sepc;
target_ulong scause;
target_ulong mtvec;
target_ulong mepc;
target_ulong mcause;
target_ulong mtval; /* since: priv-1.10.0 */
/* Hypervisor CSRs */
target_ulong hstatus;
target_ulong hedeleg;
target_ulong hideleg;
target_ulong hcounteren;
target_ulong htval;
target_ulong htinst;
target_ulong hgatp;
uint64_t htimedelta;
/* Virtual CSRs */
target_ulong vsstatus;
target_ulong vstvec;
target_ulong vsscratch;
target_ulong vsepc;
target_ulong vscause;
target_ulong vstval;
target_ulong vsatp;
#ifdef TARGET_RISCV32
target_ulong vsstatush;
#endif
target_ulong mtval2;
target_ulong mtinst;
/* HS Backup CSRs */
target_ulong stvec_hs;
target_ulong sscratch_hs;
target_ulong sepc_hs;
target_ulong scause_hs;
target_ulong stval_hs;
target_ulong satp_hs;
target_ulong mstatus_hs;
#ifdef TARGET_RISCV32
target_ulong mstatush_hs;
#endif
target_ulong scounteren;
target_ulong mcounteren;
target_ulong sscratch;
target_ulong mscratch;
/* temporary htif regs */
uint64_t mfromhost;
uint64_t mtohost;
uint64_t timecmp;
/* physical memory protection */
pmp_table_t pmp_state;
/* machine specific rdtime callback */
uint64_t (*rdtime_fn)(void);
/* True if in debugger mode. */
bool debugger;
float_status fp_status;
/* Fields from here on are preserved across CPU reset. */
QEMUTimer *timer; /* Internal timer */
// Unicorn engine
struct uc_struct *uc;
};
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A RISCV CPU model.
*/
typedef struct RISCVCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
void (*parent_reset)(CPUState *cpu);
} RISCVCPUClass;
/**
* RISCVCPU:
* @env: #CPURISCVState
*
* A RISCV CPU.
*/
typedef struct RISCVCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPURISCVState env;
/* Configuration Settings */
struct {
bool ext_i;
bool ext_e;
bool ext_g;
bool ext_m;
bool ext_a;
bool ext_f;
bool ext_d;
bool ext_c;
bool ext_s;
bool ext_u;
bool ext_h;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
char *priv_spec;
char *user_spec;
bool mmu;
bool pmp;
} cfg;
struct RISCVCPUClass cc;
} RISCVCPU;
#define RISCV_CPU(obj) ((RISCVCPU *)obj)
#define RISCV_CPU_CLASS(klass) ((RISCVCPUClass *)klass)
#define RISCV_CPU_GET_CLASS(obj) (&((RISCVCPU *)obj)->cc)
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
return (env->misa & ext) != 0;
}
static inline bool riscv_feature(CPURISCVState *env, int feature)
{
return env->features & (1ULL << feature);
}
#include "cpu_user.h"
#include "cpu_bits.h"
extern const char * const riscv_int_regnames[];
extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr);
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
#define cpu_mmu_index riscv_cpu_mmu_index
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(struct uc_struct *uc);
void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc);
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
*pc = env->pc;
*cs_base = 0;
*flags = cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
*flags |= env->mstatus & MSTATUS_FS;
}
}
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
target_ulong val)
{
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
}
static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
{
target_ulong val = 0;
riscv_csrrw(env, csrno, &val, 0, 0);
return val;
}
typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
target_ulong *ret_value);
typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
target_ulong new_value);
typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
typedef struct {
riscv_csr_predicate_fn predicate;
riscv_csr_read_fn read;
riscv_csr_write_fn write;
riscv_csr_op_fn op;
} riscv_csr_operations;
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
#endif /* RISCV_CPU_H */

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/* RISC-V ISA constants */
#ifndef TARGET_RISCV_CPU_BITS_H
#define TARGET_RISCV_CPU_BITS_H
#define get_field(reg, mask) (((reg) & \
(target_ulong)(mask)) / ((mask) & ~((mask) << 1)))
#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \
(((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \
(target_ulong)(mask)))
/* Floating point round mode */
#define FSR_RD_SHIFT 5
#define FSR_RD (0x7 << FSR_RD_SHIFT)
/* Floating point accrued exception flags */
#define FPEXC_NX 0x01
#define FPEXC_UF 0x02
#define FPEXC_OF 0x04
#define FPEXC_DZ 0x08
#define FPEXC_NV 0x10
/* Floating point status register bits */
#define FSR_AEXC_SHIFT 0
#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/* Control and Status Registers */
/* User Trap Setup */
#define CSR_USTATUS 0x000
#define CSR_UIE 0x004
#define CSR_UTVEC 0x005
/* User Trap Handling */
#define CSR_USCRATCH 0x040
#define CSR_UEPC 0x041
#define CSR_UCAUSE 0x042
#define CSR_UTVAL 0x043
#define CSR_UIP 0x044
/* User Floating-Point CSRs */
#define CSR_FFLAGS 0x001
#define CSR_FRM 0x002
#define CSR_FCSR 0x003
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
#define CSR_HPMCOUNTER3 0xc03
#define CSR_HPMCOUNTER4 0xc04
#define CSR_HPMCOUNTER5 0xc05
#define CSR_HPMCOUNTER6 0xc06
#define CSR_HPMCOUNTER7 0xc07
#define CSR_HPMCOUNTER8 0xc08
#define CSR_HPMCOUNTER9 0xc09
#define CSR_HPMCOUNTER10 0xc0a
#define CSR_HPMCOUNTER11 0xc0b
#define CSR_HPMCOUNTER12 0xc0c
#define CSR_HPMCOUNTER13 0xc0d
#define CSR_HPMCOUNTER14 0xc0e
#define CSR_HPMCOUNTER15 0xc0f
#define CSR_HPMCOUNTER16 0xc10
#define CSR_HPMCOUNTER17 0xc11
#define CSR_HPMCOUNTER18 0xc12
#define CSR_HPMCOUNTER19 0xc13
#define CSR_HPMCOUNTER20 0xc14
#define CSR_HPMCOUNTER21 0xc15
#define CSR_HPMCOUNTER22 0xc16
#define CSR_HPMCOUNTER23 0xc17
#define CSR_HPMCOUNTER24 0xc18
#define CSR_HPMCOUNTER25 0xc19
#define CSR_HPMCOUNTER26 0xc1a
#define CSR_HPMCOUNTER27 0xc1b
#define CSR_HPMCOUNTER28 0xc1c
#define CSR_HPMCOUNTER29 0xc1d
#define CSR_HPMCOUNTER30 0xc1e
#define CSR_HPMCOUNTER31 0xc1f
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
#define CSR_HPMCOUNTER3H 0xc83
#define CSR_HPMCOUNTER4H 0xc84
#define CSR_HPMCOUNTER5H 0xc85
#define CSR_HPMCOUNTER6H 0xc86
#define CSR_HPMCOUNTER7H 0xc87
#define CSR_HPMCOUNTER8H 0xc88
#define CSR_HPMCOUNTER9H 0xc89
#define CSR_HPMCOUNTER10H 0xc8a
#define CSR_HPMCOUNTER11H 0xc8b
#define CSR_HPMCOUNTER12H 0xc8c
#define CSR_HPMCOUNTER13H 0xc8d
#define CSR_HPMCOUNTER14H 0xc8e
#define CSR_HPMCOUNTER15H 0xc8f
#define CSR_HPMCOUNTER16H 0xc90
#define CSR_HPMCOUNTER17H 0xc91
#define CSR_HPMCOUNTER18H 0xc92
#define CSR_HPMCOUNTER19H 0xc93
#define CSR_HPMCOUNTER20H 0xc94
#define CSR_HPMCOUNTER21H 0xc95
#define CSR_HPMCOUNTER22H 0xc96
#define CSR_HPMCOUNTER23H 0xc97
#define CSR_HPMCOUNTER24H 0xc98
#define CSR_HPMCOUNTER25H 0xc99
#define CSR_HPMCOUNTER26H 0xc9a
#define CSR_HPMCOUNTER27H 0xc9b
#define CSR_HPMCOUNTER28H 0xc9c
#define CSR_HPMCOUNTER29H 0xc9d
#define CSR_HPMCOUNTER30H 0xc9e
#define CSR_HPMCOUNTER31H 0xc9f
/* Machine Timers and Counters */
#define CSR_MCYCLE 0xb00
#define CSR_MINSTRET 0xb02
#define CSR_MCYCLEH 0xb80
#define CSR_MINSTRETH 0xb82
/* Machine Information Registers */
#define CSR_MVENDORID 0xf11
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
/* Machine Trap Setup */
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MEDELEG 0x302
#define CSR_MIDELEG 0x303
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
/* 32-bit only */
#define CSR_MSTATUSH 0x310
/* Legacy Counter Setup (priv v1.9.1) */
/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
#define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321
#define CSR_MHCOUNTEREN 0x322
/* Machine Trap Handling */
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
/* Legacy Machine Trap Handling (priv v1.9.1) */
#define CSR_MBADADDR 0x343
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
#define CSR_SEDELEG 0x102
#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
/* Supervisor Trap Handling */
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
/* Legacy Supervisor Trap Handling (priv v1.9.1) */
#define CSR_SBADADDR 0x143
/* Supervisor Protection and Translation */
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180
/* Hpervisor CSRs */
#define CSR_HSTATUS 0x600
#define CSR_HEDELEG 0x602
#define CSR_HIDELEG 0x603
#define CSR_HIE 0x604
#define CSR_HCOUNTEREN 0x606
#define CSR_HTVAL 0x643
#define CSR_HIP 0x644
#define CSR_HTINST 0x64A
#define CSR_HGATP 0x680
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
#if defined(TARGET_RISCV32)
#define HGATP_MODE SATP32_MODE
#define HGATP_VMID SATP32_ASID
#define HGATP_PPN SATP32_PPN
#endif
#if defined(TARGET_RISCV64)
#define HGATP_MODE SATP64_MODE
#define HGATP_VMID SATP64_ASID
#define HGATP_PPN SATP64_PPN
#endif
/* Virtual CSRs */
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
#define CSR_VSTVEC 0x205
#define CSR_VSSCRATCH 0x240
#define CSR_VSEPC 0x241
#define CSR_VSCAUSE 0x242
#define CSR_VSTVAL 0x243
#define CSR_VSIP 0x244
#define CSR_VSATP 0x280
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
#define CSR_PMPCFG3 0x3a3
#define CSR_PMPADDR0 0x3b0
#define CSR_PMPADDR1 0x3b1
#define CSR_PMPADDR2 0x3b2
#define CSR_PMPADDR3 0x3b3
#define CSR_PMPADDR4 0x3b4
#define CSR_PMPADDR5 0x3b5
#define CSR_PMPADDR6 0x3b6
#define CSR_PMPADDR7 0x3b7
#define CSR_PMPADDR8 0x3b8
#define CSR_PMPADDR9 0x3b9
#define CSR_PMPADDR10 0x3ba
#define CSR_PMPADDR11 0x3bb
#define CSR_PMPADDR12 0x3bc
#define CSR_PMPADDR13 0x3bd
#define CSR_PMPADDR14 0x3be
#define CSR_PMPADDR15 0x3bf
/* Debug/Trace Registers (shared with Debug Mode) */
#define CSR_TSELECT 0x7a0
#define CSR_TDATA1 0x7a1
#define CSR_TDATA2 0x7a2
#define CSR_TDATA3 0x7a3
/* Debug Mode Registers */
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
#define CSR_DSCRATCH 0x7b2
/* Performance Counters */
#define CSR_MHPMCOUNTER3 0xb03
#define CSR_MHPMCOUNTER4 0xb04
#define CSR_MHPMCOUNTER5 0xb05
#define CSR_MHPMCOUNTER6 0xb06
#define CSR_MHPMCOUNTER7 0xb07
#define CSR_MHPMCOUNTER8 0xb08
#define CSR_MHPMCOUNTER9 0xb09
#define CSR_MHPMCOUNTER10 0xb0a
#define CSR_MHPMCOUNTER11 0xb0b
#define CSR_MHPMCOUNTER12 0xb0c
#define CSR_MHPMCOUNTER13 0xb0d
#define CSR_MHPMCOUNTER14 0xb0e
#define CSR_MHPMCOUNTER15 0xb0f
#define CSR_MHPMCOUNTER16 0xb10
#define CSR_MHPMCOUNTER17 0xb11
#define CSR_MHPMCOUNTER18 0xb12
#define CSR_MHPMCOUNTER19 0xb13
#define CSR_MHPMCOUNTER20 0xb14
#define CSR_MHPMCOUNTER21 0xb15
#define CSR_MHPMCOUNTER22 0xb16
#define CSR_MHPMCOUNTER23 0xb17
#define CSR_MHPMCOUNTER24 0xb18
#define CSR_MHPMCOUNTER25 0xb19
#define CSR_MHPMCOUNTER26 0xb1a
#define CSR_MHPMCOUNTER27 0xb1b
#define CSR_MHPMCOUNTER28 0xb1c
#define CSR_MHPMCOUNTER29 0xb1d
#define CSR_MHPMCOUNTER30 0xb1e
#define CSR_MHPMCOUNTER31 0xb1f
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
#define CSR_MHPMEVENT6 0x326
#define CSR_MHPMEVENT7 0x327
#define CSR_MHPMEVENT8 0x328
#define CSR_MHPMEVENT9 0x329
#define CSR_MHPMEVENT10 0x32a
#define CSR_MHPMEVENT11 0x32b
#define CSR_MHPMEVENT12 0x32c
#define CSR_MHPMEVENT13 0x32d
#define CSR_MHPMEVENT14 0x32e
#define CSR_MHPMEVENT15 0x32f
#define CSR_MHPMEVENT16 0x330
#define CSR_MHPMEVENT17 0x331
#define CSR_MHPMEVENT18 0x332
#define CSR_MHPMEVENT19 0x333
#define CSR_MHPMEVENT20 0x334
#define CSR_MHPMEVENT21 0x335
#define CSR_MHPMEVENT22 0x336
#define CSR_MHPMEVENT23 0x337
#define CSR_MHPMEVENT24 0x338
#define CSR_MHPMEVENT25 0x339
#define CSR_MHPMEVENT26 0x33a
#define CSR_MHPMEVENT27 0x33b
#define CSR_MHPMEVENT28 0x33c
#define CSR_MHPMEVENT29 0x33d
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
#define CSR_MHPMCOUNTER3H 0xb83
#define CSR_MHPMCOUNTER4H 0xb84
#define CSR_MHPMCOUNTER5H 0xb85
#define CSR_MHPMCOUNTER6H 0xb86
#define CSR_MHPMCOUNTER7H 0xb87
#define CSR_MHPMCOUNTER8H 0xb88
#define CSR_MHPMCOUNTER9H 0xb89
#define CSR_MHPMCOUNTER10H 0xb8a
#define CSR_MHPMCOUNTER11H 0xb8b
#define CSR_MHPMCOUNTER12H 0xb8c
#define CSR_MHPMCOUNTER13H 0xb8d
#define CSR_MHPMCOUNTER14H 0xb8e
#define CSR_MHPMCOUNTER15H 0xb8f
#define CSR_MHPMCOUNTER16H 0xb90
#define CSR_MHPMCOUNTER17H 0xb91
#define CSR_MHPMCOUNTER18H 0xb92
#define CSR_MHPMCOUNTER19H 0xb93
#define CSR_MHPMCOUNTER20H 0xb94
#define CSR_MHPMCOUNTER21H 0xb95
#define CSR_MHPMCOUNTER22H 0xb96
#define CSR_MHPMCOUNTER23H 0xb97
#define CSR_MHPMCOUNTER24H 0xb98
#define CSR_MHPMCOUNTER25H 0xb99
#define CSR_MHPMCOUNTER26H 0xb9a
#define CSR_MHPMCOUNTER27H 0xb9b
#define CSR_MHPMCOUNTER28H 0xb9c
#define CSR_MHPMCOUNTER29H 0xb9d
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
/* Legacy Machine Protection and Translation (priv v1.9.1) */
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
#define CSR_MIBASE 0x382
#define CSR_MIBOUND 0x383
#define CSR_MDBASE 0x384
#define CSR_MDBOUND 0x385
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
#define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000
#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
#define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */
#define MSTATUS_MXR 0x00080000
#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
#if defined(TARGET_RISCV64)
#define MSTATUS_MTL 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
#elif defined(TARGET_RISCV32)
#define MSTATUS_MTL 0x00000040
#define MSTATUS_MPV 0x00000080
#endif
#ifdef TARGET_RISCV32
# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV)
#else
# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV)
#endif
#define MSTATUS64_UXL 0x0000000300000000ULL
#define MSTATUS64_SXL 0x0000000C00000000ULL
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000ULL
#define MISA32_MXL 0xC0000000
#define MISA64_MXL 0xC000000000000000ULL
#define MXL_RV32 1
#define MXL_RV64 2
#define MXL_RV128 3
#if defined(TARGET_RISCV32)
#define MSTATUS_SD MSTATUS32_SD
#define MISA_MXL MISA32_MXL
#define MXL_VAL MXL_RV32
#elif defined(TARGET_RISCV64)
#define MSTATUS_SD MSTATUS64_SD
#define MISA_MXL MISA64_MXL
#define MXL_VAL MXL_RV64
#endif
/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_SPP 0x00000100
#define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000
#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
#define SSTATUS_MXR 0x00080000
#define SSTATUS32_SD 0x80000000
#define SSTATUS64_SD 0x8000000000000000ULL
#if defined(TARGET_RISCV32)
#define SSTATUS_SD SSTATUS32_SD
#elif defined(TARGET_RISCV64)
#define SSTATUS_SD SSTATUS64_SD
#endif
/* hstatus CSR bits */
#define HSTATUS_SPRV 0x00000001
#define HSTATUS_SPV 0x00000080
#define HSTATUS_SP2P 0x00000100
#define HSTATUS_SP2V 0x00000200
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
#if defined(TARGET_RISCV32)
#define HSTATUS_WPRI HSTATUS32_WPRI
#elif defined(TARGET_RISCV64)
#define HSTATUS_WPRI HSTATUS64_WPRI
#endif
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
#define PRV_H 2 /* Reserved */
#define PRV_M 3
/* Virtulisation Register Fields */
#define VIRT_ONOFF 1
/* This is used to save state for when we take an exception. If this is set
* that means that we want to force a HS level exception (no matter what the
* delegation is set to). This will occur for things such as a second level
* page table fault.
*/
#define FORCE_HS_EXCEP 2
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000
#define SATP32_PPN 0x003fffff
/* RV64 satp CSR field masks */
#define SATP64_MODE 0xF000000000000000ULL
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
#if defined(TARGET_RISCV32)
#define SATP_MODE SATP32_MODE
#define SATP_ASID SATP32_ASID
#define SATP_PPN SATP32_PPN
#endif
#if defined(TARGET_RISCV64)
#define SATP_MODE SATP64_MODE
#define SATP_ASID SATP64_ASID
#define SATP_PPN SATP64_PPN
#endif
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
#define VM_1_09_MBARE 0
#define VM_1_09_MBB 1
#define VM_1_09_MBBID 2
#define VM_1_09_SV32 8
#define VM_1_09_SV39 9
#define VM_1_09_SV48 10
/* VM modes (satp.mode) privileged ISA 1.10 */
#define VM_1_10_MBARE 0
#define VM_1_10_SV32 1
#define VM_1_10_SV39 8
#define VM_1_10_SV48 9
#define VM_1_10_SV57 10
#define VM_1_10_SV64 11
/* Page table entry (PTE) fields */
#define PTE_V 0x001 /* Valid */
#define PTE_R 0x002 /* Read */
#define PTE_W 0x004 /* Write */
#define PTE_X 0x008 /* Execute */
#define PTE_U 0x010 /* User */
#define PTE_G 0x020 /* Global */
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
/* Leaf page shift amount */
#define PGSHIFT 12
/* Default Reset Vector adress */
#define DEFAULT_RSTVEC 0x1000
/* Exception causes */
#define EXCP_NONE -1 /* sentinel value */
#define RISCV_EXCP_INST_ADDR_MIS 0x0
#define RISCV_EXCP_INST_ACCESS_FAULT 0x1
#define RISCV_EXCP_ILLEGAL_INST 0x2
#define RISCV_EXCP_BREAKPOINT 0x3
#define RISCV_EXCP_LOAD_ADDR_MIS 0x4
#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
#define RISCV_EXCP_U_ECALL 0x8
#define RISCV_EXCP_S_ECALL 0x9
#define RISCV_EXCP_VS_ECALL 0xa
#define RISCV_EXCP_M_ECALL 0xb
#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */
#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */
#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
#define RISCV_EXCP_UNICORN_END 0x8888
#define RISCV_EXCP_INT_FLAG 0x80000000
#define RISCV_EXCP_INT_MASK 0x7fffffff
/* Interrupt causes */
#define IRQ_U_SOFT 0
#define IRQ_S_SOFT 1
#define IRQ_VS_SOFT 2
#define IRQ_M_SOFT 3
#define IRQ_U_TIMER 4
#define IRQ_S_TIMER 5
#define IRQ_VS_TIMER 6
#define IRQ_M_TIMER 7
#define IRQ_U_EXT 8
#define IRQ_S_EXT 9
#define IRQ_VS_EXT 10
#define IRQ_M_EXT 11
/* mip masks */
#define MIP_USIP (1 << IRQ_U_SOFT)
#define MIP_SSIP (1 << IRQ_S_SOFT)
#define MIP_VSSIP (1 << IRQ_VS_SOFT)
#define MIP_MSIP (1 << IRQ_M_SOFT)
#define MIP_UTIP (1 << IRQ_U_TIMER)
#define MIP_STIP (1 << IRQ_S_TIMER)
#define MIP_VSTIP (1 << IRQ_VS_TIMER)
#define MIP_MTIP (1 << IRQ_M_TIMER)
#define MIP_UEIP (1 << IRQ_U_EXT)
#define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_VSEIP (1 << IRQ_VS_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)
/* sip masks */
#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP
#define SIP_SEIP MIP_SEIP
/* MIE masks */
#define MIE_SEIE (1 << IRQ_S_EXT)
#define MIE_UEIE (1 << IRQ_U_EXT)
#define MIE_STIE (1 << IRQ_S_TIMER)
#define MIE_UTIE (1 << IRQ_U_TIMER)
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
#endif

978
qemu/target/riscv/cpu_helper.c Normal file
View File

@@ -0,0 +1,978 @@
/*
* RISC-V CPU helpers for qemu.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
return env->priv;
}
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
target_ulong irqs;
target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE);
target_ulong pending = env->mip & env->mie &
~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
target_ulong vspending = (env->mip & env->mie &
(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
target_ulong mie = env->priv < PRV_M ||
(env->priv == PRV_M && mstatus_mie);
target_ulong sie = env->priv < PRV_S ||
(env->priv == PRV_S && mstatus_sie);
target_ulong hs_sie = env->priv < PRV_S ||
(env->priv == PRV_S && hs_mstatus_sie);
if (riscv_cpu_virt_enabled(env)) {
#ifdef _MSC_VER
target_ulong pending_hs_irq = pending & (0 - hs_sie);
#else
target_ulong pending_hs_irq = pending & -hs_sie;
#endif
if (pending_hs_irq) {
riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
return ctz64(pending_hs_irq);
}
pending = vspending;
}
#ifdef _MSC_VER
irqs = (pending & ~env->mideleg & (0 - mie)) | (pending & env->mideleg & (0 - sie));
#else
irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie);
#endif
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
return EXCP_NONE; /* indicates no pending interrupt */
}
}
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
int interruptno = riscv_cpu_local_irq_pending(env);
if (interruptno >= 0) {
cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
riscv_cpu_do_interrupt(cs);
return true;
}
}
return false;
}
/* Return true is floating point support is currently enabled */
bool riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (env->mstatus & MSTATUS_FS) {
if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
return false;
}
return true;
}
return false;
}
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE;
bool current_virt = riscv_cpu_virt_enabled(env);
g_assert(riscv_has_ext(env, RVH));
#if defined(TARGET_RISCV64)
mstatus_mask |= MSTATUS64_UXL;
#endif
if (current_virt) {
/* Current V=1 and we are about to change to V=0 */
env->vsstatus = env->mstatus & mstatus_mask;
env->mstatus &= ~mstatus_mask;
env->mstatus |= env->mstatus_hs;
#if defined(TARGET_RISCV32)
env->vsstatush = env->mstatush;
env->mstatush |= env->mstatush_hs;
#endif
env->vstvec = env->stvec;
env->stvec = env->stvec_hs;
env->vsscratch = env->sscratch;
env->sscratch = env->sscratch_hs;
env->vsepc = env->sepc;
env->sepc = env->sepc_hs;
env->vscause = env->scause;
env->scause = env->scause_hs;
env->vstval = env->sbadaddr;
env->sbadaddr = env->stval_hs;
env->vsatp = env->satp;
env->satp = env->satp_hs;
} else {
/* Current V=0 and we are about to change to V=1 */
env->mstatus_hs = env->mstatus & mstatus_mask;
env->mstatus &= ~mstatus_mask;
env->mstatus |= env->vsstatus;
#if defined(TARGET_RISCV32)
env->mstatush_hs = env->mstatush;
env->mstatush |= env->vsstatush;
#endif
env->stvec_hs = env->stvec;
env->stvec = env->vstvec;
env->sscratch_hs = env->sscratch;
env->sscratch = env->vsscratch;
env->sepc_hs = env->sepc;
env->sepc = env->vsepc;
env->scause_hs = env->scause;
env->scause = env->vscause;
env->stval_hs = env->sbadaddr;
env->sbadaddr = env->vstval;
env->satp_hs = env->satp;
env->satp = env->vsatp;
}
}
bool riscv_cpu_virt_enabled(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
return false;
}
return get_field(env->virt, VIRT_ONOFF);
}
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
{
if (!riscv_has_ext(env, RVH)) {
return;
}
/* Flush the TLB on all virt mode changes. */
if (get_field(env->virt, VIRT_ONOFF) != enable) {
tlb_flush(env_cpu(env));
}
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
}
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
return false;
}
return get_field(env->virt, FORCE_HS_EXCEP);
}
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
{
if (!riscv_has_ext(env, RVH)) {
return;
}
env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
if (env->miclaim & interrupts) {
return -1;
} else {
env->miclaim |= interrupts;
return 0;
}
}
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
{
CPURISCVState *env = &cpu->env;
CPUState *cs = CPU(cpu);
uint32_t old = env->mip;
env->mip = (env->mip & ~mask) | (value & mask);
if (env->mip) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
return old;
}
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
{
env->rdtime_fn = fn;
}
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {
g_assert_not_reached();
}
if (newpriv == PRV_H) {
newpriv = PRV_U;
}
/* tlb_flush is unnecessary as mode is contained in mmu_idx */
env->priv = newpriv;
/*
* Clear the load reservation - otherwise a reservation placed in one
* context/process can be used by another, resulting in an SC succeeding
* incorrectly. Version 2.2 of the ISA specification explicitly requires
* this behaviour, while later revisions say that the kernel "should" use
* an SC instruction to force the yielding of a load reservation on a
* preemptive context switch. As a result, do both.
*/
env->load_res = -1;
}
/* get_physical_address - get the physical address for this virtual address
*
* Do a page table walk to obtain the physical address corresponding to a
* virtual address. Returns 0 if the translation was successful
*
* Adapted from Spike's mmu_t::translate and mmu_t::walk
*
* @env: CPURISCVState
* @physical: This will be set to the calculated physical address
* @prot: The returned protection attributes
* @addr: The virtual address to be translated
* @access_type: The type of MMU access
* @mmu_idx: Indicates current privilege level
* @first_stage: Are we in first stage translation?
* Second stage is used for hypervisor guest translation
* @two_stage: Are we going to perform two stage translation
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int *prot, target_ulong addr,
int access_type, int mmu_idx,
bool first_stage, bool two_stage)
{
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
* (riscv_cpu_do_interrupt) is correct */
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmu_idx;
bool use_background = false;
hwaddr base;
int levels = 0, ptidxbits = 0, ptesize = 0, vm, sum, mxr, widened;
/*
* Check if we should use the background registers for the two
* stage translation. We don't need to check if we actually need
* two stage translation as that happened before this function
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
if (riscv_has_ext(env, RVH) &&
MSTATUS_MPV_ISSET(env)) {
use_background = true;
}
}
}
if (mode == PRV_S && access_type != MMU_INST_FETCH &&
riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
if (get_field(env->hstatus, HSTATUS_SPRV)) {
mode = get_field(env->mstatus, SSTATUS_SPP);
use_background = true;
}
}
if (first_stage == false) {
/* We are in stage 2 translation, this is similar to stage 1. */
/* Stage 2 is always taken as U-mode */
mode = PRV_U;
}
if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
}
*prot = 0;
if (first_stage == true) {
mxr = get_field(env->mstatus, MSTATUS_MXR);
} else {
mxr = get_field(env->vsstatus, MSTATUS_MXR);
}
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
if (first_stage == true) {
if (use_background) {
base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
vm = get_field(env->vsatp, SATP_MODE);
} else {
base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP_MODE);
}
widened = 0;
} else {
base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
vm = get_field(env->hgatp, HGATP_MODE);
widened = 2;
}
sum = get_field(env->mstatus, MSTATUS_SUM);
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
case VM_1_10_SV39:
levels = 3; ptidxbits = 9; ptesize = 8; break;
case VM_1_10_SV48:
levels = 4; ptidxbits = 9; ptesize = 8; break;
case VM_1_10_SV57:
levels = 5; ptidxbits = 9; ptesize = 8; break;
case VM_1_10_MBARE:
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
default:
g_assert_not_reached();
}
} else {
widened = 0;
base = (hwaddr)(env->sptbr) << PGSHIFT;
sum = !get_field(env->mstatus, MSTATUS_PUM);
vm = get_field(env->mstatus, MSTATUS_VM);
switch (vm) {
case VM_1_09_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
case VM_1_09_SV39:
levels = 3; ptidxbits = 9; ptesize = 8; break;
case VM_1_09_SV48:
levels = 4; ptidxbits = 9; ptesize = 8; break;
case VM_1_09_MBARE:
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
default:
g_assert_not_reached();
}
}
CPUState *cs = env_cpu(env);
int va_bits = PGSHIFT + levels * ptidxbits + widened;
target_ulong mask, masked_msbs;
if (TARGET_LONG_BITS > (va_bits - 1)) {
mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
} else {
mask = 0;
}
masked_msbs = (addr >> (va_bits - 1)) & mask;
if (masked_msbs != 0 && masked_msbs != mask) {
return TRANSLATE_FAIL;
}
int ptshift = (levels - 1) * ptidxbits;
int i;
#if !TCG_OVERSIZED_GUEST
restart:
#endif
for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
target_ulong idx;
if (i == 0) {
idx = (addr >> (PGSHIFT + ptshift)) &
((1 << (ptidxbits + widened)) - 1);
} else {
idx = (addr >> (PGSHIFT + ptshift)) &
((1 << ptidxbits) - 1);
}
/* check that physical address of PTE is legal */
hwaddr pte_addr;
if (two_stage && first_stage) {
hwaddr vbase;
/* Do the second stage translation on the base PTE address. */
get_physical_address(env, &vbase, prot, base, access_type,
mmu_idx, false, true);
pte_addr = vbase + idx * ptesize;
} else {
pte_addr = base + idx * ptesize;
}
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
1 << MMU_DATA_LOAD, PRV_S)) {
return TRANSLATE_PMP_FAIL;
}
#if defined(TARGET_RISCV32)
#ifdef UNICORN_ARCH_POSTFIX
target_ulong pte = glue(address_space_ldl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, pte_addr, attrs, &res);
#else
target_ulong pte = address_space_ldl(cs->as->uc, cs->as, pte_addr, attrs, &res);
#endif
#elif defined(TARGET_RISCV64)
#ifdef UNICORN_ARCH_POSTFIX
target_ulong pte = glue(address_space_ldq, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, pte_addr, attrs, &res);
#else
target_ulong pte = address_space_ldq(cs->as->uc, cs->as, pte_addr, attrs, &res);
#endif
#endif
if (res != MEMTX_OK) {
return TRANSLATE_FAIL;
}
hwaddr ppn = pte >> PTE_PPN_SHIFT;
if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
return TRANSLATE_FAIL;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
/* Reserved leaf PTE flags: PTE_W + PTE_X */
return TRANSLATE_FAIL;
} else if ((pte & PTE_U) && ((mode != PRV_U) &&
(!sum || access_type == MMU_INST_FETCH))) {
/* User PTE flags when not U mode and mstatus.SUM is not set,
or the access type is an instruction fetch */
return TRANSLATE_FAIL;
} else if (!(pte & PTE_U) && (mode != PRV_S)) {
/* Supervisor PTE flags when not S mode */
return TRANSLATE_FAIL;
} else if (ppn & ((1ULL << ptshift) - 1)) {
/* Misaligned PPN */
return TRANSLATE_FAIL;
} else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
((pte & PTE_X) && mxr))) {
/* Read access check failed */
return TRANSLATE_FAIL;
} else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
/* Write access check failed */
return TRANSLATE_FAIL;
} else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
/* Fetch access check failed */
return TRANSLATE_FAIL;
} else {
/* if necessary, set accessed and dirty bits. */
target_ulong updated_pte = pte | PTE_A |
(access_type == MMU_DATA_STORE ? PTE_D : 0);
/* Page table updates need to be atomic with MTTCG enabled */
if (updated_pte != pte) {
/*
* - if accessed or dirty bits need updating, and the PTE is
* in RAM, then we do so atomically with a compare and swap.
* - if the PTE is in IO space or ROM, then it can't be updated
* and we return TRANSLATE_FAIL.
* - if the PTE changed by the time we went to update it, then
* it is no longer valid and we must re-walk the page table.
*/
MemoryRegion *mr;
hwaddr l = sizeof(target_ulong), addr1;
mr = address_space_translate(cs->as, pte_addr,
&addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
if (memory_region_is_ram(mr)) {
target_ulong *pte_pa =
qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
#if TCG_OVERSIZED_GUEST
/* MTTCG is not enabled on oversized TCG guests so
* page table updates do not need to be atomic */
*pte_pa = pte = updated_pte;
#else
target_ulong old_pte =
#ifdef _MSC_VER
atomic_cmpxchg((long *)pte_pa, pte, updated_pte);
#else
atomic_cmpxchg(pte_pa, pte, updated_pte);
#endif
if (old_pte != pte) {
goto restart;
} else {
pte = updated_pte;
}
#endif
} else {
/* misconfigured PTE in ROM (AD bits are not preset) or
* PTE is in IO space and can't be updated atomically */
return TRANSLATE_FAIL;
}
}
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
target_ulong vpn = addr >> PGSHIFT;
if (i == 0) {
*physical = (ppn | (vpn & ((1L << (ptshift + widened)) - 1))) <<
PGSHIFT;
} else {
*physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
}
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
*prot |= PAGE_READ;
}
if ((pte & PTE_X)) {
*prot |= PAGE_EXEC;
}
/* add write permission on stores or if the page is already dirty,
so that we TLB miss on later writes to update the dirty bit */
if ((pte & PTE_W) &&
(access_type == MMU_DATA_STORE || (pte & PTE_D))) {
*prot |= PAGE_WRITE;
}
return TRANSLATE_SUCCESS;
}
}
return TRANSLATE_FAIL;
}
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
MMUAccessType access_type, bool pmp_violation,
bool first_stage)
{
CPUState *cs = env_cpu(env);
int page_fault_exceptions;
if (first_stage) {
page_fault_exceptions =
(env->priv_ver >= PRIV_VERSION_1_10_0) &&
get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
!pmp_violation;
} else {
page_fault_exceptions =
get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
!pmp_violation;
}
switch (access_type) {
case MMU_INST_FETCH:
if (riscv_cpu_virt_enabled(env) && !first_stage) {
cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
}
break;
case MMU_DATA_LOAD:
if (riscv_cpu_virt_enabled(env) && !first_stage) {
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
}
break;
case MMU_DATA_STORE:
if (riscv_cpu_virt_enabled(env) && !first_stage) {
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
}
break;
default:
g_assert_not_reached();
}
env->badaddr = address;
}
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
hwaddr phys_addr;
int prot;
int mmu_idx = cpu_mmu_index(&cpu->env, false);
if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx,
true, riscv_cpu_virt_enabled(env))) {
return -1;
}
if (riscv_cpu_virt_enabled(env)) {
if (get_physical_address(env, &phys_addr, &prot, phys_addr,
0, mmu_idx, false, true)) {
return -1;
}
}
return phys_addr;
}
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
if (access_type == MMU_DATA_STORE) {
cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
} else {
cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
}
env->badaddr = addr;
riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
}
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
break;
case MMU_DATA_LOAD:
cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
break;
case MMU_DATA_STORE:
cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
break;
default:
g_assert_not_reached();
}
env->badaddr = addr;
riscv_raise_exception(env, cs->exception_index, retaddr);
}
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
vaddr im_address;
hwaddr pa = 0;
int prot;
bool pmp_violation = false;
bool m_mode_two_stage = false;
bool hs_mode_two_stage = false;
bool first_stage_error = true;
int ret = TRANSLATE_FAIL;
int mode = mmu_idx;
env->guest_phys_fault_addr = 0;
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
/*
* Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
* set and we want to access a virtulisation address.
*/
if (riscv_has_ext(env, RVH)) {
m_mode_two_stage = env->priv == PRV_M &&
access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV) &&
MSTATUS_MPV_ISSET(env);
hs_mode_two_stage = env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
access_type != MMU_INST_FETCH &&
get_field(env->hstatus, HSTATUS_SPRV) &&
get_field(env->hstatus, HSTATUS_SPV);
}
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
}
}
if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address, access_type,
mmu_idx, true, true);
qemu_log_mask(CPU_LOG_MMU,
"%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
TARGET_FMT_plx " prot %d\n",
__func__, address, ret, pa, prot);
if (ret != TRANSLATE_FAIL) {
/* Second stage lookup */
im_address = pa;
ret = get_physical_address(env, &pa, &prot, im_address,
access_type, mmu_idx, false, true);
qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
TARGET_FMT_plx " prot %d\n",
__func__, im_address, ret, pa, prot);
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
ret = TRANSLATE_PMP_FAIL;
}
if (ret != TRANSLATE_SUCCESS) {
/*
* Guest physical address translation failed, this is a HS
* level exception
*/
first_stage_error = false;
env->guest_phys_fault_addr = (im_address |
(address &
(TARGET_PAGE_SIZE - 1))) >> 2;
}
}
} else {
/* Single stage lookup */
ret = get_physical_address(env, &pa, &prot, address, access_type,
mmu_idx, true, false);
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical "
TARGET_FMT_plx " prot %d\n",
__func__, address, ret, pa, prot);
}
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
ret = TRANSLATE_PMP_FAIL;
}
if (ret == TRANSLATE_PMP_FAIL) {
pmp_violation = true;
}
if (ret == TRANSLATE_SUCCESS) {
tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return true;
} else if (probe) {
return false;
} else {
raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
return true;
}
/*
* Handle Traps
*
* Adapted from Spike's processor_t::take_trap.
*
*/
void riscv_cpu_do_interrupt(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
target_ulong s;
/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
* so we mask off the MSB and separate into trap type and cause.
*/
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
target_ulong deleg = async ? env->mideleg : env->medeleg;
target_ulong tval = 0;
target_ulong htval = 0;
target_ulong mtval2 = 0;
if (!async) {
/* set tval to badaddr for traps with address information */
switch (cause) {
case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
force_hs_execp = true;
/* fallthrough */
case RISCV_EXCP_INST_ADDR_MIS:
case RISCV_EXCP_INST_ACCESS_FAULT:
case RISCV_EXCP_LOAD_ADDR_MIS:
case RISCV_EXCP_STORE_AMO_ADDR_MIS:
case RISCV_EXCP_LOAD_ACCESS_FAULT:
case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
case RISCV_EXCP_INST_PAGE_FAULT:
case RISCV_EXCP_LOAD_PAGE_FAULT:
case RISCV_EXCP_STORE_PAGE_FAULT:
tval = env->badaddr;
break;
default:
break;
}
/* ecall is dispatched as one cause so translate based on mode */
if (cause == RISCV_EXCP_U_ECALL) {
assert(env->priv <= 3);
if (env->priv == PRV_M) {
cause = RISCV_EXCP_M_ECALL;
} else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
cause = RISCV_EXCP_VS_ECALL;
} else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
cause = RISCV_EXCP_S_ECALL;
} else if (env->priv == PRV_U) {
cause = RISCV_EXCP_U_ECALL;
}
}
}
if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
/* handle the trap in S-mode */
if (riscv_has_ext(env, RVH)) {
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
* no if hypervisor has delegated one of hs mode's interrupt
*/
if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
cause == IRQ_VS_EXT)
cause = cause - 1;
/* Trap to VS mode */
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
riscv_cpu_swap_hypervisor_regs(env);
env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
get_field(env->hstatus, HSTATUS_SPV));
env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
get_field(env->mstatus, SSTATUS_SPP));
env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
riscv_cpu_virt_enabled(env));
htval = env->guest_phys_fault_addr;
riscv_cpu_set_virt_enabled(env, 0);
riscv_cpu_set_force_hs_excep(env, 0);
} else {
/* Trap into HS mode */
env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
get_field(env->hstatus, HSTATUS_SPV));
env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
get_field(env->mstatus, SSTATUS_SPP));
env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
riscv_cpu_virt_enabled(env));
htval = env->guest_phys_fault_addr;
}
}
s = env->mstatus;
s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
env->sepc = env->pc;
env->sbadaddr = tval;
env->htval = htval;
env->pc = (env->stvec >> 2 << 2) +
((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_S);
} else {
/* handle the trap in M-mode */
if (riscv_has_ext(env, RVH)) {
if (riscv_cpu_virt_enabled(env)) {
riscv_cpu_swap_hypervisor_regs(env);
}
#ifdef TARGET_RISCV32
env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
riscv_cpu_virt_enabled(env));
env->mstatush = set_field(env->mstatush, MSTATUS_MTL,
riscv_cpu_force_hs_excep_enabled(env));
#else
env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
riscv_cpu_virt_enabled(env));
env->mstatus = set_field(env->mstatus, MSTATUS_MTL,
riscv_cpu_force_hs_excep_enabled(env));
#endif
mtval2 = env->guest_phys_fault_addr;
/* Trapping to M mode, virt is disabled */
riscv_cpu_set_virt_enabled(env, 0);
riscv_cpu_set_force_hs_excep(env, 0);
}
s = env->mstatus;
s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
env->mcause = cause | ~(((target_ulong)-1) >> async);
env->mepc = env->pc;
env->mbadaddr = tval;
env->mtval2 = mtval2;
env->pc = (env->mtvec >> 2 << 2) +
((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_M);
}
/* NOTE: it is not necessary to yield load reservations here. It is only
* necessary for an SC from "another hart" to cause a load reservation
* to be yielded. Refer to the memory consistency model section of the
* RISC-V ISA Specification.
*/
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
}

19
qemu/target/riscv/cpu_user.h Normal file
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@@ -0,0 +1,19 @@
#ifndef TARGET_RISCV_CPU_USER_H
#define TARGET_RISCV_CPU_USER_H
#define xRA 1 /* return address (aka link register) */
#define xSP 2 /* stack pointer */
#define xGP 3 /* global pointer */
#define xTP 4 /* thread pointer */
#define xA0 10 /* gpr[10-17] are syscall arguments */
#define xA1 11
#define xA2 12
#define xA3 13
#define xA4 14
#define xA5 15
#define xA6 16
#define xA7 17 /* syscall number for RVI ABI */
#define xT0 5 /* syscall number for RVE ABI */
#endif

1604
qemu/target/riscv/csr.c Normal file
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File diff suppressed because it is too large Load Diff

371
qemu/target/riscv/fpu_helper.c Normal file
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@@ -0,0 +1,371 @@
/*
* RISC-V FPU Emulation Helpers for QEMU.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
{
int soft = get_float_exception_flags(&env->fp_status);
target_ulong hard = 0;
hard |= (soft & float_flag_inexact) ? FPEXC_NX : 0;
hard |= (soft & float_flag_underflow) ? FPEXC_UF : 0;
hard |= (soft & float_flag_overflow) ? FPEXC_OF : 0;
hard |= (soft & float_flag_divbyzero) ? FPEXC_DZ : 0;
hard |= (soft & float_flag_invalid) ? FPEXC_NV : 0;
return hard;
}
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
{
int soft = 0;
soft |= (hard & FPEXC_NX) ? float_flag_inexact : 0;
soft |= (hard & FPEXC_UF) ? float_flag_underflow : 0;
soft |= (hard & FPEXC_OF) ? float_flag_overflow : 0;
soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0;
soft |= (hard & FPEXC_NV) ? float_flag_invalid : 0;
set_float_exception_flags(soft, &env->fp_status);
}
void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
{
int softrm;
if (rm == 7) {
rm = env->frm;
}
switch (rm) {
case 0:
softrm = float_round_nearest_even;
break;
case 1:
softrm = float_round_to_zero;
break;
case 2:
softrm = float_round_down;
break;
case 3:
softrm = float_round_up;
break;
case 4:
softrm = float_round_ties_away;
break;
default:
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
set_float_rounding_mode(softrm, &env->fp_status);
}
uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
return float32_muladd(frs1, frs2, frs3, 0, &env->fp_status);
}
uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status);
}
uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c,
&env->fp_status);
}
uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c,
&env->fp_status);
}
uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
return float32_muladd(frs1, frs2, frs3, float_muladd_negate_product,
&env->fp_status);
}
uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
return float64_muladd(frs1, frs2, frs3, float_muladd_negate_product,
&env->fp_status);
}
uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c |
float_muladd_negate_product, &env->fp_status);
}
uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c |
float_muladd_negate_product, &env->fp_status);
}
uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float32_add(frs1, frs2, &env->fp_status);
}
uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float32_sub(frs1, frs2, &env->fp_status);
}
uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float32_mul(frs1, frs2, &env->fp_status);
}
uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float32_div(frs1, frs2, &env->fp_status);
}
uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float32_minnum(frs1, frs2, &env->fp_status);
}
uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float32_maxnum(frs1, frs2, &env->fp_status);
}
uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1)
{
return float32_sqrt(frs1, &env->fp_status);
}
target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float32_le(frs1, frs2, &env->fp_status);
}
target_ulong helper_flt_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float32_lt(frs1, frs2, &env->fp_status);
}
target_ulong helper_feq_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float32_eq_quiet(frs1, frs2, &env->fp_status);
}
target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t frs1)
{
return float32_to_int32(frs1, &env->fp_status);
}
target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t frs1)
{
return (int32_t)float32_to_uint32(frs1, &env->fp_status);
}
#if defined(TARGET_RISCV64)
uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t frs1)
{
return float32_to_int64(frs1, &env->fp_status);
}
uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t frs1)
{
return float32_to_uint64(frs1, &env->fp_status);
}
#endif
uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1)
{
return int32_to_float32((int32_t)rs1, &env->fp_status);
}
uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
{
return uint32_to_float32((uint32_t)rs1, &env->fp_status);
}
#if defined(TARGET_RISCV64)
uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
{
return int64_to_float32(rs1, &env->fp_status);
}
uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
{
return uint64_to_float32(rs1, &env->fp_status);
}
#endif
target_ulong helper_fclass_s(uint64_t frs1)
{
float32 f = frs1;
bool sign = float32_is_neg(f);
if (float32_is_infinity(f)) {
return sign ? 1 << 0 : 1 << 7;
} else if (float32_is_zero(f)) {
return sign ? 1 << 3 : 1 << 4;
} else if (float32_is_zero_or_denormal(f)) {
return sign ? 1 << 2 : 1 << 5;
} else if (float32_is_any_nan(f)) {
float_status s = { 0 }; /* for snan_bit_is_one */
return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
} else {
return sign ? 1 << 1 : 1 << 6;
}
}
uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float64_add(frs1, frs2, &env->fp_status);
}
uint64_t helper_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float64_sub(frs1, frs2, &env->fp_status);
}
uint64_t helper_fmul_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float64_mul(frs1, frs2, &env->fp_status);
}
uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float64_div(frs1, frs2, &env->fp_status);
}
uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float64_minnum(frs1, frs2, &env->fp_status);
}
uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float64_maxnum(frs1, frs2, &env->fp_status);
}
uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
{
return float64_to_float32(rs1, &env->fp_status);
}
uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1)
{
return float32_to_float64(rs1, &env->fp_status);
}
uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1)
{
return float64_sqrt(frs1, &env->fp_status);
}
target_ulong helper_fle_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float64_le(frs1, frs2, &env->fp_status);
}
target_ulong helper_flt_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float64_lt(frs1, frs2, &env->fp_status);
}
target_ulong helper_feq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
return float64_eq_quiet(frs1, frs2, &env->fp_status);
}
target_ulong helper_fcvt_w_d(CPURISCVState *env, uint64_t frs1)
{
return float64_to_int32(frs1, &env->fp_status);
}
target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
{
return (int32_t)float64_to_uint32(frs1, &env->fp_status);
}
#if defined(TARGET_RISCV64)
uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
{
return float64_to_int64(frs1, &env->fp_status);
}
uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
{
return float64_to_uint64(frs1, &env->fp_status);
}
#endif
uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1)
{
return int32_to_float64((int32_t)rs1, &env->fp_status);
}
uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
{
return uint32_to_float64((uint32_t)rs1, &env->fp_status);
}
#if defined(TARGET_RISCV64)
uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
{
return int64_to_float64(rs1, &env->fp_status);
}
uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
{
return uint64_to_float64(rs1, &env->fp_status);
}
#endif
target_ulong helper_fclass_d(uint64_t frs1)
{
float64 f = frs1;
bool sign = float64_is_neg(f);
if (float64_is_infinity(f)) {
return sign ? 1 << 0 : 1 << 7;
} else if (float64_is_zero(f)) {
return sign ? 1 << 3 : 1 << 4;
} else if (float64_is_zero_or_denormal(f)) {
return sign ? 1 << 2 : 1 << 5;
} else if (float64_is_any_nan(f)) {
float_status s = { 0 }; /* for snan_bit_is_one */
return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
} else {
return sign ? 1 << 1 : 1 << 6;
}
}

79
qemu/target/riscv/helper.h Normal file
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DEF_HELPER_4(uc_tracecode, void, i32, i32, ptr, i64)
DEF_HELPER_1(uc_riscv_exit, void, env)
/* Exceptions */
DEF_HELPER_2(raise_exception, noreturn, env, i32)
/* Floating Point - rounding mode */
DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
/* Floating Point - fused */
DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fnmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fnmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fnmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fnmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
/* Floating Point - Single Precision */
DEF_HELPER_FLAGS_3(fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fdiv_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmin_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmax_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_2(fsqrt_s, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_3(fle_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
#endif
DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
#endif
DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
/* Floating Point - Double Precision */
DEF_HELPER_FLAGS_3(fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmul_d, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fdiv_d, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmin_d, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmax_d, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_s_d, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_d_s, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fsqrt_d, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_3(fle_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
#endif
DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
#endif
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
DEF_HELPER_4(csrrc, tl, env, tl, tl, tl)
DEF_HELPER_2(sret, tl, env, tl)
DEF_HELPER_2(mret, tl, env, tl)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env)

133
qemu/target/riscv/insn_trans/trans_privileged.inc.c Normal file
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/*
* RISC-V translation routines for the RISC-V privileged instructions.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
{
/* always generates U-level ECALL, fixed in do_interrupt handler */
generate_exception(ctx, RISCV_EXCP_U_ECALL);
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
{
// ignore this instruction
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
static bool trans_uret(DisasContext *ctx, arg_uret *a)
{
return false;
}
static bool trans_sret(DisasContext *ctx, arg_sret *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, ctx->base.pc_next);
if (has_ext(ctx, RVS)) {
gen_helper_sret(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->cpu_env, tcg_ctx->cpu_pc);
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
} else {
return false;
}
return true;
}
static bool trans_mret(DisasContext *ctx, arg_mret *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, ctx->base.pc_next);
gen_helper_mret(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->cpu_env, tcg_ctx->cpu_pc);
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, ctx->pc_succ_insn);
gen_helper_wfi(tcg_ctx, tcg_ctx->cpu_env);
return true;
}
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (ctx->priv_ver >= PRIV_VERSION_1_10_0) {
gen_helper_tlb_flush(tcg_ctx, tcg_ctx->cpu_env);
return true;
}
return false;
}
static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
gen_helper_tlb_flush(tcg_ctx, tcg_ctx->cpu_env);
return true;
}
return false;
}
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
* (env->priv == PRV_S &&
* !riscv_cpu_virt_enabled(env) &&
* get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
*/
gen_helper_tlb_flush(tcg_ctx, tcg_ctx->cpu_env);
return true;
/* } */
}
return false;
}
static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
* (env->priv == PRV_S &&
* !riscv_cpu_virt_enabled(env) &&
* get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
*/
gen_helper_tlb_flush(tcg_ctx, tcg_ctx->cpu_env);
return true;
/* } */
}
return false;
}

227
qemu/target/riscv/insn_trans/trans_rva.inc.c Normal file
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@@ -0,0 +1,227 @@
/*
* RISC-V translation routines for the RV64A Standard Extension.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv src1 = tcg_temp_new(tcg_ctx);
/* Put addr in load_res, data in load_val. */
gen_get_gpr(tcg_ctx, src1, a->rs1);
if (a->rl) {
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_STRL);
}
tcg_gen_qemu_ld_tl(tcg_ctx, tcg_ctx->load_val, src1, ctx->mem_idx, mop);
if (a->aq) {
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_LDAQ);
}
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->load_res, src1);
gen_set_gpr(tcg_ctx, a->rd, tcg_ctx->load_val);
tcg_temp_free(tcg_ctx, src1);
return true;
}
static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv src1 = tcg_temp_new(tcg_ctx);
TCGv src2 = tcg_temp_new(tcg_ctx);
TCGv dat = tcg_temp_new(tcg_ctx);
TCGLabel *l1 = gen_new_label(tcg_ctx);
TCGLabel *l2 = gen_new_label(tcg_ctx);
gen_get_gpr(tcg_ctx, src1, a->rs1);
tcg_gen_brcond_tl(tcg_ctx, TCG_COND_NE, tcg_ctx->load_res, src1, l1);
gen_get_gpr(tcg_ctx, src2, a->rs2);
/*
* Note that the TCG atomic primitives are SC,
* so we can ignore AQ/RL along this path.
*/
tcg_gen_atomic_cmpxchg_tl(tcg_ctx, src1, tcg_ctx->load_res, tcg_ctx->load_val, src2,
ctx->mem_idx, mop);
tcg_gen_setcond_tl(tcg_ctx, TCG_COND_NE, dat, src1, tcg_ctx->load_val);
gen_set_gpr(tcg_ctx, a->rd, dat);
tcg_gen_br(tcg_ctx, l2);
gen_set_label(tcg_ctx, l1);
/*
* Address comparison failure. However, we still need to
* provide the memory barrier implied by AQ/RL.
*/
tcg_gen_mb(tcg_ctx, TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
tcg_gen_movi_tl(tcg_ctx, dat, 1);
gen_set_gpr(tcg_ctx, a->rd, dat);
gen_set_label(tcg_ctx, l2);
/*
* Clear the load reservation, since an SC must fail if there is
* an SC to any address, in between an LR and SC pair.
*/
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->load_res, -1);
tcg_temp_free(tcg_ctx, dat);
tcg_temp_free(tcg_ctx, src1);
tcg_temp_free(tcg_ctx, src2);
return true;
}
static bool gen_amo(DisasContext *ctx, arg_atomic *a,
void(*func)(TCGContext *, TCGv, TCGv, TCGv, TCGArg, MemOp),
MemOp mop)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv src1 = tcg_temp_new(tcg_ctx);
TCGv src2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, src1, a->rs1);
gen_get_gpr(tcg_ctx, src2, a->rs2);
(*func)(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(tcg_ctx, a->rd, src2);
tcg_temp_free(tcg_ctx, src1);
tcg_temp_free(tcg_ctx, src2);
return true;
}
static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
}
static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
}
static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
}
static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
}
#ifdef TARGET_RISCV64
static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
{
return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
}
static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
{
return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
}
static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
}
#endif

473
qemu/target/riscv/insn_trans/trans_rvd.inc.c Normal file
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/*
* RISC-V translation routines for the RV64D Standard Extension.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool trans_fld(DisasContext *ctx, arg_fld *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_ld_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
mark_fs_dirty(ctx);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fmadd_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2], tcg_ctx->cpu_fpr[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fmsub_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2], tcg_ctx->cpu_fpr[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fnmsub_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2], tcg_ctx->cpu_fpr[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fnmadd_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2], tcg_ctx->cpu_fpr[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fadd_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fsub_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fmul_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fdiv_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fsqrt_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (a->rs1 == a->rs2) { /* FMOV */
tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs1]);
} else {
tcg_gen_deposit_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs2],
tcg_ctx->cpu_fpr[a->rs1], 0, 63);
}
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (a->rs1 == a->rs2) { /* FNEG */
tcg_gen_xori_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs1], INT64_MIN);
} else {
TCGv_i64 t0 = tcg_temp_new_i64(tcg_ctx);
tcg_gen_not_i64(tcg_ctx, t0, tcg_ctx->cpu_fpr[a->rs2]);
tcg_gen_deposit_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], t0, tcg_ctx->cpu_fpr[a->rs1], 0, 63);
tcg_temp_free_i64(tcg_ctx, t0);
}
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (a->rs1 == a->rs2) { /* FABS */
tcg_gen_andi_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs1], ~INT64_MIN);
} else {
TCGv_i64 t0 = tcg_temp_new_i64(tcg_ctx);
tcg_gen_andi_i64(tcg_ctx, t0, tcg_ctx->cpu_fpr[a->rs2], INT64_MIN);
tcg_gen_xor_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs1], t0);
tcg_temp_free_i64(tcg_ctx, t0);
}
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_helper_fmin_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_helper_fmax_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_d(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_feq_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_flt_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_fle_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_fclass_d(tcg_ctx, t0, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_w_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_wu_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_w(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, t0);
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_wu(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, t0);
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);
return true;
}
#ifdef TARGET_RISCV64
static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_l_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_lu_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_gpr(tcg_ctx, a->rd, tcg_ctx->cpu_fpr[a->rs1]);
return true;
}
static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_l(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, t0);
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_d_lu(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, t0);
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], t0);
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);
return true;
}
#endif

474
qemu/target/riscv/insn_trans/trans_rvf.inc.c Normal file
View File

@@ -0,0 +1,474 @@
/*
* RISC-V translation routines for the RV64F Standard Extension.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define REQUIRE_FPU do {\
if (ctx->mstatus_fs == 0) \
return false; \
} while (0)
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_ld_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
/* RISC-V requires NaN-boxing of narrower width floating point values */
tcg_gen_ori_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rd], 0xffffffff00000000ULL);
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fmadd_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2], tcg_ctx->cpu_fpr[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fmsub_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2], tcg_ctx->cpu_fpr[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fnmsub_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2], tcg_ctx->cpu_fpr[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fnmadd_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2], tcg_ctx->cpu_fpr[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fadd_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fsub_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fmul_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fdiv_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_set_rm(ctx, a->rm);
gen_helper_fsqrt_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (a->rs1 == a->rs2) { /* FMOV */
tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs1]);
} else { /* FSGNJ */
tcg_gen_deposit_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs2], tcg_ctx->cpu_fpr[a->rs1],
0, 31);
}
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (a->rs1 == a->rs2) { /* FNEG */
tcg_gen_xori_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs1], INT32_MIN);
} else {
TCGv_i64 t0 = tcg_temp_new_i64(tcg_ctx);
tcg_gen_not_i64(tcg_ctx, t0, tcg_ctx->cpu_fpr[a->rs2]);
tcg_gen_deposit_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], t0, tcg_ctx->cpu_fpr[a->rs1], 0, 31);
tcg_temp_free_i64(tcg_ctx, t0);
}
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (a->rs1 == a->rs2) { /* FABS */
tcg_gen_andi_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs1], ~INT32_MIN);
} else {
TCGv_i64 t0 = tcg_temp_new_i64(tcg_ctx);
tcg_gen_andi_i64(tcg_ctx, t0, tcg_ctx->cpu_fpr[a->rs2], INT32_MIN);
tcg_gen_xor_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_fpr[a->rs1], t0);
tcg_temp_free_i64(tcg_ctx, t0);
}
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_helper_fmin_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
gen_helper_fmax_s(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1],
tcg_ctx->cpu_fpr[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_w_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_wu_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
{
/* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
#if defined(TARGET_RISCV64)
tcg_gen_ext32s_tl(tcg_ctx, t0, tcg_ctx->cpu_fpr[a->rs1]);
#else
tcg_gen_extrl_i64_i32(tcg_ctx, t0, tcg_ctx->cpu_fpr[a->rs1]);
#endif
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_feq_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_flt_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_fle_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1], tcg_ctx->cpu_fpr[a->rs2]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_fclass_s(tcg_ctx, t0, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_w(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, t0);
mark_fs_dirty(ctx);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_wu(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, t0);
mark_fs_dirty(ctx);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
{
/* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
#if defined(TARGET_RISCV64)
tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], t0);
#else
tcg_gen_extu_i32_i64(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], t0);
#endif
mark_fs_dirty(ctx);
tcg_temp_free(tcg_ctx, t0);
return true;
}
#ifdef TARGET_RISCV64
static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_l_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_lu_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr[a->rs1]);
gen_set_gpr(tcg_ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_l(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, t0);
mark_fs_dirty(ctx);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_lu(tcg_ctx, tcg_ctx->cpu_fpr[a->rd], tcg_ctx->cpu_env, t0);
mark_fs_dirty(ctx);
tcg_temp_free(tcg_ctx, t0);
return true;
}
#endif

613
qemu/target/riscv/insn_trans/trans_rvi.inc.c Normal file
View File

@@ -0,0 +1,613 @@
/*
* RISC-V translation routines for the RVXI Base Integer Instruction Set.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool trans_illegal(DisasContext *ctx, arg_empty *a)
{
gen_exception_illegal(ctx);
return true;
}
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[a->rd], a->imm);
}
return true;
}
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
if (a->rd != 0) {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
}
return true;
}
static bool trans_jal(DisasContext *ctx, arg_jal *a)
{
gen_jal(ctx, a->rd, a->imm);
return true;
}
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/* no chaining with JALR */
TCGLabel *misaligned = NULL;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, tcg_ctx->cpu_pc, a->rs1);
tcg_gen_addi_tl(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->cpu_pc, a->imm);
tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->cpu_pc, (target_ulong)-2);
if (!has_ext(ctx, RVC)) {
misaligned = gen_new_label(tcg_ctx);
tcg_gen_andi_tl(tcg_ctx, t0, tcg_ctx->cpu_pc, 0x2);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, 0x0, misaligned);
}
if (a->rd != 0) {
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[a->rd], ctx->pc_succ_insn);
}
lookup_and_goto_ptr(ctx);
if (misaligned) {
gen_set_label(tcg_ctx, misaligned);
gen_exception_inst_addr_mis(ctx);
}
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGLabel *l = gen_new_label(tcg_ctx);
TCGv source1, source2;
source1 = tcg_temp_new(tcg_ctx);
source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
tcg_gen_brcond_tl(tcg_ctx, cond, source1, source2, l);
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
gen_set_label(tcg_ctx, l); /* branch taken */
if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
}
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
static bool trans_beq(DisasContext *ctx, arg_beq *a)
{
return gen_branch(ctx, a, TCG_COND_EQ);
}
static bool trans_bne(DisasContext *ctx, arg_bne *a)
{
return gen_branch(ctx, a, TCG_COND_NE);
}
static bool trans_blt(DisasContext *ctx, arg_blt *a)
{
return gen_branch(ctx, a, TCG_COND_LT);
}
static bool trans_bge(DisasContext *ctx, arg_bge *a)
{
return gen_branch(ctx, a, TCG_COND_GE);
}
static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
{
return gen_branch(ctx, a, TCG_COND_LTU);
}
static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
{
return gen_branch(ctx, a, TCG_COND_GEU);
}
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
TCGv t1 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_ld_tl(tcg_ctx, t1, t0, ctx->mem_idx, memop);
gen_set_gpr(tcg_ctx, a->rd, t1);
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
return true;
}
static bool trans_lb(DisasContext *ctx, arg_lb *a)
{
return gen_load(ctx, a, MO_SB);
}
static bool trans_lh(DisasContext *ctx, arg_lh *a)
{
return gen_load(ctx, a, MO_TESW);
}
static bool trans_lw(DisasContext *ctx, arg_lw *a)
{
return gen_load(ctx, a, MO_TESL);
}
static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
{
return gen_load(ctx, a, MO_UB);
}
static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
{
return gen_load(ctx, a, MO_TEUW);
}
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
TCGv dat = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, a->rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
gen_get_gpr(tcg_ctx, dat, a->rs2);
tcg_gen_qemu_st_tl(tcg_ctx, dat, t0, ctx->mem_idx, memop);
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, dat);
return true;
}
static bool trans_sb(DisasContext *ctx, arg_sb *a)
{
return gen_store(ctx, a, MO_SB);
}
static bool trans_sh(DisasContext *ctx, arg_sh *a)
{
return gen_store(ctx, a, MO_TESW);
}
static bool trans_sw(DisasContext *ctx, arg_sw *a)
{
return gen_store(ctx, a, MO_TESL);
}
#ifdef TARGET_RISCV64
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
return gen_load(ctx, a, MO_TEUL);
}
static bool trans_ld(DisasContext *ctx, arg_ld *a)
{
return gen_load(ctx, a, MO_TEQ);
}
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
return gen_store(ctx, a, MO_TEQ);
}
#endif
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
}
static void gen_slt(TCGContext *tcg_ctx, TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LT, ret, s1, s2);
}
static void gen_sltu(TCGContext *tcg_ctx, TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LTU, ret, s1, s2);
}
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
return gen_arith_imm_tl(ctx, a, &gen_slt);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
return gen_arith_imm_tl(ctx, a, &gen_sltu);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (a->shamt >= TARGET_LONG_BITS) {
return false;
}
if (a->rd != 0) {
TCGv t = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t, a->rs1);
tcg_gen_shli_tl(tcg_ctx, t, t, a->shamt);
gen_set_gpr(tcg_ctx, a->rd, t);
tcg_temp_free(tcg_ctx, t);
} /* NOP otherwise */
return true;
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (a->shamt >= TARGET_LONG_BITS) {
return false;
}
if (a->rd != 0) {
TCGv t = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t, a->rs1);
tcg_gen_shri_tl(tcg_ctx, t, t, a->shamt);
gen_set_gpr(tcg_ctx, a->rd, t);
tcg_temp_free(tcg_ctx, t);
} /* NOP otherwise */
return true;
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (a->shamt >= TARGET_LONG_BITS) {
return false;
}
if (a->rd != 0) {
TCGv t = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t, a->rs1);
tcg_gen_sari_tl(tcg_ctx, t, t, a->shamt);
gen_set_gpr(tcg_ctx, a->rd, t);
tcg_temp_free(tcg_ctx, t);
} /* NOP otherwise */
return true;
}
static bool trans_add(DisasContext *ctx, arg_add *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
return gen_shift(ctx, a, &tcg_gen_shl_tl);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
return gen_shift(ctx, a, &tcg_gen_shr_tl);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
return gen_shift(ctx, a, &tcg_gen_sar_tl);
}
static bool trans_or(DisasContext *ctx, arg_or *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
return gen_arith_imm_tl(ctx, a, &gen_addw);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1;
source1 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
tcg_gen_shli_tl(tcg_ctx, source1, source1, a->shamt);
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
return true;
}
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t, a->rs1);
tcg_gen_extract_tl(tcg_ctx, t, t, a->shamt, 32 - a->shamt);
/* sign-extend for W instructions */
tcg_gen_ext32s_tl(tcg_ctx, t, t);
gen_set_gpr(tcg_ctx, a->rd, t);
tcg_temp_free(tcg_ctx, t);
return true;
}
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t, a->rs1);
tcg_gen_sextract_tl(tcg_ctx, t, t, a->shamt, 32 - a->shamt);
gen_set_gpr(tcg_ctx, a->rd, t);
tcg_temp_free(tcg_ctx, t);
return true;
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1 = tcg_temp_new(tcg_ctx);
TCGv source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F);
tcg_gen_shl_tl(tcg_ctx, source1, source1, source2);
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1 = tcg_temp_new(tcg_ctx);
TCGv source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
/* clear upper 32 */
tcg_gen_ext32u_tl(tcg_ctx, source1, source1);
tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F);
tcg_gen_shr_tl(tcg_ctx, source1, source1, source2);
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1 = tcg_temp_new(tcg_ctx);
TCGv source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
/*
* first, trick to get it to act like working on 32 bits (get rid of
* upper 32, sign extend to fill space)
*/
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F);
tcg_gen_sar_tl(tcg_ctx, source1, source1, source2);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
#endif
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/* FENCE is a full memory barrier. */
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_SC);
return true;
}
static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (!ctx->ext_ifencei) {
return false;
}
/*
* FENCE_I is a no-op in QEMU,
* however we need to end the translation block
*/
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, ctx->pc_succ_insn);
exit_tb(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
#define RISCV_OP_CSR_PRE do {\
source1 = tcg_temp_new(tcg_ctx); \
csr_store = tcg_temp_new(tcg_ctx); \
dest = tcg_temp_new(tcg_ctx); \
rs1_pass = tcg_temp_new(tcg_ctx); \
gen_get_gpr(tcg_ctx, source1, a->rs1); \
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, ctx->base.pc_next); \
tcg_gen_movi_tl(tcg_ctx, rs1_pass, a->rs1); \
tcg_gen_movi_tl(tcg_ctx, csr_store, a->csr); \
gen_io_start(tcg_ctx);\
} while (0)
#define RISCV_OP_CSR_POST do {\
gen_set_gpr(tcg_ctx, a->rd, dest); \
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, ctx->pc_succ_insn); \
exit_tb(ctx); \
ctx->base.is_jmp = DISAS_NORETURN; \
tcg_temp_free(tcg_ctx, source1); \
tcg_temp_free(tcg_ctx, csr_store); \
tcg_temp_free(tcg_ctx, dest); \
tcg_temp_free(tcg_ctx, rs1_pass); \
} while (0)
static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1, csr_store, dest, rs1_pass;
RISCV_OP_CSR_PRE;
gen_helper_csrrw(tcg_ctx, dest, tcg_ctx->cpu_env, source1, csr_store);
RISCV_OP_CSR_POST;
return true;
}
static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1, csr_store, dest, rs1_pass;
RISCV_OP_CSR_PRE;
gen_helper_csrrs(tcg_ctx, dest, tcg_ctx->cpu_env, source1, csr_store, rs1_pass);
RISCV_OP_CSR_POST;
return true;
}
static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1, csr_store, dest, rs1_pass;
RISCV_OP_CSR_PRE;
gen_helper_csrrc(tcg_ctx, dest, tcg_ctx->cpu_env, source1, csr_store, rs1_pass);
RISCV_OP_CSR_POST;
return true;
}
static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1, csr_store, dest, rs1_pass;
RISCV_OP_CSR_PRE;
gen_helper_csrrw(tcg_ctx, dest, tcg_ctx->cpu_env, rs1_pass, csr_store);
RISCV_OP_CSR_POST;
return true;
}
static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1, csr_store, dest, rs1_pass;
RISCV_OP_CSR_PRE;
gen_helper_csrrs(tcg_ctx, dest, tcg_ctx->cpu_env, rs1_pass, csr_store, rs1_pass);
RISCV_OP_CSR_POST;
return true;
}
static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1, csr_store, dest, rs1_pass;
RISCV_OP_CSR_PRE;
gen_helper_csrrc(tcg_ctx, dest, tcg_ctx->cpu_env, rs1_pass, csr_store, rs1_pass);
RISCV_OP_CSR_POST;
return true;
}

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/*
* RISC-V translation routines for the RV64M Standard Extension.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_EXT(ctx, RVM);
TCGv source1 = tcg_temp_new(tcg_ctx);
TCGv source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
tcg_gen_muls2_tl(tcg_ctx, source2, source1, source1, source2);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_EXT(ctx, RVM);
TCGv source1 = tcg_temp_new(tcg_ctx);
TCGv source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
tcg_gen_mulu2_tl(tcg_ctx, source2, source1, source1, source2);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
static bool trans_div(DisasContext *ctx, arg_div *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_remu);
}
#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith(tcg_ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith_div_w(tcg_ctx, a, &gen_div);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith_div_uw(tcg_ctx, a, &gen_divu);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith_div_w(tcg_ctx, a, &gen_rem);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
REQUIRE_EXT(ctx, RVM);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
return gen_arith_div_uw(tcg_ctx, a, &gen_remu);
}
#endif

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/*
* RISC-V emulation for qemu: Instruction decode helpers
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef TARGET_RISCV_INSTMAP_H
#define TARGET_RISCV_INSTMAP_H
#define MASK_OP_MAJOR(op) (op & 0x7F)
enum {
/* rv32i, rv64i, rv32m */
OPC_RISC_LUI = (0x37),
OPC_RISC_AUIPC = (0x17),
OPC_RISC_JAL = (0x6F),
OPC_RISC_JALR = (0x67),
OPC_RISC_BRANCH = (0x63),
OPC_RISC_LOAD = (0x03),
OPC_RISC_STORE = (0x23),
OPC_RISC_ARITH_IMM = (0x13),
OPC_RISC_ARITH = (0x33),
OPC_RISC_FENCE = (0x0F),
OPC_RISC_SYSTEM = (0x73),
/* rv64i, rv64m */
OPC_RISC_ARITH_IMM_W = (0x1B),
OPC_RISC_ARITH_W = (0x3B),
/* rv32a, rv64a */
OPC_RISC_ATOMIC = (0x2F),
/* floating point */
OPC_RISC_FP_LOAD = (0x7),
OPC_RISC_FP_STORE = (0x27),
OPC_RISC_FMADD = (0x43),
OPC_RISC_FMSUB = (0x47),
OPC_RISC_FNMSUB = (0x4B),
OPC_RISC_FNMADD = (0x4F),
OPC_RISC_FP_ARITH = (0x53),
};
#define MASK_OP_ARITH(op) (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | \
(0x7F << 25))))
enum {
OPC_RISC_ADD = OPC_RISC_ARITH | (0x0 << 12) | (0x00 << 25),
OPC_RISC_SUB = OPC_RISC_ARITH | (0x0 << 12) | (0x20 << 25),
OPC_RISC_SLL = OPC_RISC_ARITH | (0x1 << 12) | (0x00 << 25),
OPC_RISC_SLT = OPC_RISC_ARITH | (0x2 << 12) | (0x00 << 25),
OPC_RISC_SLTU = OPC_RISC_ARITH | (0x3 << 12) | (0x00 << 25),
OPC_RISC_XOR = OPC_RISC_ARITH | (0x4 << 12) | (0x00 << 25),
OPC_RISC_SRL = OPC_RISC_ARITH | (0x5 << 12) | (0x00 << 25),
OPC_RISC_SRA = OPC_RISC_ARITH | (0x5 << 12) | (0x20 << 25),
OPC_RISC_OR = OPC_RISC_ARITH | (0x6 << 12) | (0x00 << 25),
OPC_RISC_AND = OPC_RISC_ARITH | (0x7 << 12) | (0x00 << 25),
/* RV64M */
OPC_RISC_MUL = OPC_RISC_ARITH | (0x0 << 12) | (0x01 << 25),
OPC_RISC_MULH = OPC_RISC_ARITH | (0x1 << 12) | (0x01 << 25),
OPC_RISC_MULHSU = OPC_RISC_ARITH | (0x2 << 12) | (0x01 << 25),
OPC_RISC_MULHU = OPC_RISC_ARITH | (0x3 << 12) | (0x01 << 25),
OPC_RISC_DIV = OPC_RISC_ARITH | (0x4 << 12) | (0x01 << 25),
OPC_RISC_DIVU = OPC_RISC_ARITH | (0x5 << 12) | (0x01 << 25),
OPC_RISC_REM = OPC_RISC_ARITH | (0x6 << 12) | (0x01 << 25),
OPC_RISC_REMU = OPC_RISC_ARITH | (0x7 << 12) | (0x01 << 25),
};
#define MASK_OP_ARITH_IMM(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
OPC_RISC_ADDI = OPC_RISC_ARITH_IMM | (0x0 << 12),
OPC_RISC_SLTI = OPC_RISC_ARITH_IMM | (0x2 << 12),
OPC_RISC_SLTIU = OPC_RISC_ARITH_IMM | (0x3 << 12),
OPC_RISC_XORI = OPC_RISC_ARITH_IMM | (0x4 << 12),
OPC_RISC_ORI = OPC_RISC_ARITH_IMM | (0x6 << 12),
OPC_RISC_ANDI = OPC_RISC_ARITH_IMM | (0x7 << 12),
OPC_RISC_SLLI = OPC_RISC_ARITH_IMM | (0x1 << 12), /* additional part of
IMM */
OPC_RISC_SHIFT_RIGHT_I = OPC_RISC_ARITH_IMM | (0x5 << 12) /* SRAI, SRLI */
};
#define MASK_OP_BRANCH(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
OPC_RISC_BEQ = OPC_RISC_BRANCH | (0x0 << 12),
OPC_RISC_BNE = OPC_RISC_BRANCH | (0x1 << 12),
OPC_RISC_BLT = OPC_RISC_BRANCH | (0x4 << 12),
OPC_RISC_BGE = OPC_RISC_BRANCH | (0x5 << 12),
OPC_RISC_BLTU = OPC_RISC_BRANCH | (0x6 << 12),
OPC_RISC_BGEU = OPC_RISC_BRANCH | (0x7 << 12)
};
enum {
OPC_RISC_ADDIW = OPC_RISC_ARITH_IMM_W | (0x0 << 12),
OPC_RISC_SLLIW = OPC_RISC_ARITH_IMM_W | (0x1 << 12), /* additional part of
IMM */
OPC_RISC_SHIFT_RIGHT_IW = OPC_RISC_ARITH_IMM_W | (0x5 << 12) /* SRAI, SRLI
*/
};
enum {
OPC_RISC_ADDW = OPC_RISC_ARITH_W | (0x0 << 12) | (0x00 << 25),
OPC_RISC_SUBW = OPC_RISC_ARITH_W | (0x0 << 12) | (0x20 << 25),
OPC_RISC_SLLW = OPC_RISC_ARITH_W | (0x1 << 12) | (0x00 << 25),
OPC_RISC_SRLW = OPC_RISC_ARITH_W | (0x5 << 12) | (0x00 << 25),
OPC_RISC_SRAW = OPC_RISC_ARITH_W | (0x5 << 12) | (0x20 << 25),
/* RV64M */
OPC_RISC_MULW = OPC_RISC_ARITH_W | (0x0 << 12) | (0x01 << 25),
OPC_RISC_DIVW = OPC_RISC_ARITH_W | (0x4 << 12) | (0x01 << 25),
OPC_RISC_DIVUW = OPC_RISC_ARITH_W | (0x5 << 12) | (0x01 << 25),
OPC_RISC_REMW = OPC_RISC_ARITH_W | (0x6 << 12) | (0x01 << 25),
OPC_RISC_REMUW = OPC_RISC_ARITH_W | (0x7 << 12) | (0x01 << 25),
};
#define MASK_OP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
OPC_RISC_LB = OPC_RISC_LOAD | (0x0 << 12),
OPC_RISC_LH = OPC_RISC_LOAD | (0x1 << 12),
OPC_RISC_LW = OPC_RISC_LOAD | (0x2 << 12),
OPC_RISC_LD = OPC_RISC_LOAD | (0x3 << 12),
OPC_RISC_LBU = OPC_RISC_LOAD | (0x4 << 12),
OPC_RISC_LHU = OPC_RISC_LOAD | (0x5 << 12),
OPC_RISC_LWU = OPC_RISC_LOAD | (0x6 << 12),
};
#define MASK_OP_STORE(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
OPC_RISC_SB = OPC_RISC_STORE | (0x0 << 12),
OPC_RISC_SH = OPC_RISC_STORE | (0x1 << 12),
OPC_RISC_SW = OPC_RISC_STORE | (0x2 << 12),
OPC_RISC_SD = OPC_RISC_STORE | (0x3 << 12),
};
#define MASK_OP_JALR(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
/* no enum since OPC_RISC_JALR is the actual value */
#define MASK_OP_ATOMIC(op) \
(MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | (0x7F << 25))))
#define MASK_OP_ATOMIC_NO_AQ_RL_SZ(op) \
(MASK_OP_MAJOR(op) | (op & (0x1F << 27)))
enum {
OPC_RISC_LR = OPC_RISC_ATOMIC | (0x02 << 27),
OPC_RISC_SC = OPC_RISC_ATOMIC | (0x03 << 27),
OPC_RISC_AMOSWAP = OPC_RISC_ATOMIC | (0x01 << 27),
OPC_RISC_AMOADD = OPC_RISC_ATOMIC | (0x00 << 27),
OPC_RISC_AMOXOR = OPC_RISC_ATOMIC | (0x04 << 27),
OPC_RISC_AMOAND = OPC_RISC_ATOMIC | (0x0C << 27),
OPC_RISC_AMOOR = OPC_RISC_ATOMIC | (0x08 << 27),
OPC_RISC_AMOMIN = OPC_RISC_ATOMIC | (0x10 << 27),
OPC_RISC_AMOMAX = OPC_RISC_ATOMIC | (0x14 << 27),
OPC_RISC_AMOMINU = OPC_RISC_ATOMIC | (0x18 << 27),
OPC_RISC_AMOMAXU = OPC_RISC_ATOMIC | (0x1C << 27),
};
#define MASK_OP_SYSTEM(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
OPC_RISC_ECALL = OPC_RISC_SYSTEM | (0x0 << 12),
OPC_RISC_EBREAK = OPC_RISC_SYSTEM | (0x0 << 12),
OPC_RISC_ERET = OPC_RISC_SYSTEM | (0x0 << 12),
OPC_RISC_MRTS = OPC_RISC_SYSTEM | (0x0 << 12),
OPC_RISC_MRTH = OPC_RISC_SYSTEM | (0x0 << 12),
OPC_RISC_HRTS = OPC_RISC_SYSTEM | (0x0 << 12),
OPC_RISC_WFI = OPC_RISC_SYSTEM | (0x0 << 12),
OPC_RISC_SFENCEVM = OPC_RISC_SYSTEM | (0x0 << 12),
OPC_RISC_CSRRW = OPC_RISC_SYSTEM | (0x1 << 12),
OPC_RISC_CSRRS = OPC_RISC_SYSTEM | (0x2 << 12),
OPC_RISC_CSRRC = OPC_RISC_SYSTEM | (0x3 << 12),
OPC_RISC_CSRRWI = OPC_RISC_SYSTEM | (0x5 << 12),
OPC_RISC_CSRRSI = OPC_RISC_SYSTEM | (0x6 << 12),
OPC_RISC_CSRRCI = OPC_RISC_SYSTEM | (0x7 << 12),
};
#define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
OPC_RISC_FLW = OPC_RISC_FP_LOAD | (0x2 << 12),
OPC_RISC_FLD = OPC_RISC_FP_LOAD | (0x3 << 12),
};
#define MASK_OP_FP_STORE(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
OPC_RISC_FSW = OPC_RISC_FP_STORE | (0x2 << 12),
OPC_RISC_FSD = OPC_RISC_FP_STORE | (0x3 << 12),
};
#define MASK_OP_FP_FMADD(op) (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
enum {
OPC_RISC_FMADD_S = OPC_RISC_FMADD | (0x0 << 25),
OPC_RISC_FMADD_D = OPC_RISC_FMADD | (0x1 << 25),
};
#define MASK_OP_FP_FMSUB(op) (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
enum {
OPC_RISC_FMSUB_S = OPC_RISC_FMSUB | (0x0 << 25),
OPC_RISC_FMSUB_D = OPC_RISC_FMSUB | (0x1 << 25),
};
#define MASK_OP_FP_FNMADD(op) (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
enum {
OPC_RISC_FNMADD_S = OPC_RISC_FNMADD | (0x0 << 25),
OPC_RISC_FNMADD_D = OPC_RISC_FNMADD | (0x1 << 25),
};
#define MASK_OP_FP_FNMSUB(op) (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
enum {
OPC_RISC_FNMSUB_S = OPC_RISC_FNMSUB | (0x0 << 25),
OPC_RISC_FNMSUB_D = OPC_RISC_FNMSUB | (0x1 << 25),
};
#define MASK_OP_FP_ARITH(op) (MASK_OP_MAJOR(op) | (op & (0x7F << 25)))
enum {
/* float */
OPC_RISC_FADD_S = OPC_RISC_FP_ARITH | (0x0 << 25),
OPC_RISC_FSUB_S = OPC_RISC_FP_ARITH | (0x4 << 25),
OPC_RISC_FMUL_S = OPC_RISC_FP_ARITH | (0x8 << 25),
OPC_RISC_FDIV_S = OPC_RISC_FP_ARITH | (0xC << 25),
OPC_RISC_FSGNJ_S = OPC_RISC_FP_ARITH | (0x10 << 25),
OPC_RISC_FSGNJN_S = OPC_RISC_FP_ARITH | (0x10 << 25),
OPC_RISC_FSGNJX_S = OPC_RISC_FP_ARITH | (0x10 << 25),
OPC_RISC_FMIN_S = OPC_RISC_FP_ARITH | (0x14 << 25),
OPC_RISC_FMAX_S = OPC_RISC_FP_ARITH | (0x14 << 25),
OPC_RISC_FSQRT_S = OPC_RISC_FP_ARITH | (0x2C << 25),
OPC_RISC_FEQ_S = OPC_RISC_FP_ARITH | (0x50 << 25),
OPC_RISC_FLT_S = OPC_RISC_FP_ARITH | (0x50 << 25),
OPC_RISC_FLE_S = OPC_RISC_FP_ARITH | (0x50 << 25),
OPC_RISC_FCVT_W_S = OPC_RISC_FP_ARITH | (0x60 << 25),
OPC_RISC_FCVT_WU_S = OPC_RISC_FP_ARITH | (0x60 << 25),
OPC_RISC_FCVT_L_S = OPC_RISC_FP_ARITH | (0x60 << 25),
OPC_RISC_FCVT_LU_S = OPC_RISC_FP_ARITH | (0x60 << 25),
OPC_RISC_FCVT_S_W = OPC_RISC_FP_ARITH | (0x68 << 25),
OPC_RISC_FCVT_S_WU = OPC_RISC_FP_ARITH | (0x68 << 25),
OPC_RISC_FCVT_S_L = OPC_RISC_FP_ARITH | (0x68 << 25),
OPC_RISC_FCVT_S_LU = OPC_RISC_FP_ARITH | (0x68 << 25),
OPC_RISC_FMV_X_S = OPC_RISC_FP_ARITH | (0x70 << 25),
OPC_RISC_FCLASS_S = OPC_RISC_FP_ARITH | (0x70 << 25),
OPC_RISC_FMV_S_X = OPC_RISC_FP_ARITH | (0x78 << 25),
/* double */
OPC_RISC_FADD_D = OPC_RISC_FP_ARITH | (0x1 << 25),
OPC_RISC_FSUB_D = OPC_RISC_FP_ARITH | (0x5 << 25),
OPC_RISC_FMUL_D = OPC_RISC_FP_ARITH | (0x9 << 25),
OPC_RISC_FDIV_D = OPC_RISC_FP_ARITH | (0xD << 25),
OPC_RISC_FSGNJ_D = OPC_RISC_FP_ARITH | (0x11 << 25),
OPC_RISC_FSGNJN_D = OPC_RISC_FP_ARITH | (0x11 << 25),
OPC_RISC_FSGNJX_D = OPC_RISC_FP_ARITH | (0x11 << 25),
OPC_RISC_FMIN_D = OPC_RISC_FP_ARITH | (0x15 << 25),
OPC_RISC_FMAX_D = OPC_RISC_FP_ARITH | (0x15 << 25),
OPC_RISC_FCVT_S_D = OPC_RISC_FP_ARITH | (0x20 << 25),
OPC_RISC_FCVT_D_S = OPC_RISC_FP_ARITH | (0x21 << 25),
OPC_RISC_FSQRT_D = OPC_RISC_FP_ARITH | (0x2D << 25),
OPC_RISC_FEQ_D = OPC_RISC_FP_ARITH | (0x51 << 25),
OPC_RISC_FLT_D = OPC_RISC_FP_ARITH | (0x51 << 25),
OPC_RISC_FLE_D = OPC_RISC_FP_ARITH | (0x51 << 25),
OPC_RISC_FCVT_W_D = OPC_RISC_FP_ARITH | (0x61 << 25),
OPC_RISC_FCVT_WU_D = OPC_RISC_FP_ARITH | (0x61 << 25),
OPC_RISC_FCVT_L_D = OPC_RISC_FP_ARITH | (0x61 << 25),
OPC_RISC_FCVT_LU_D = OPC_RISC_FP_ARITH | (0x61 << 25),
OPC_RISC_FCVT_D_W = OPC_RISC_FP_ARITH | (0x69 << 25),
OPC_RISC_FCVT_D_WU = OPC_RISC_FP_ARITH | (0x69 << 25),
OPC_RISC_FCVT_D_L = OPC_RISC_FP_ARITH | (0x69 << 25),
OPC_RISC_FCVT_D_LU = OPC_RISC_FP_ARITH | (0x69 << 25),
OPC_RISC_FMV_X_D = OPC_RISC_FP_ARITH | (0x71 << 25),
OPC_RISC_FCLASS_D = OPC_RISC_FP_ARITH | (0x71 << 25),
OPC_RISC_FMV_D_X = OPC_RISC_FP_ARITH | (0x79 << 25),
};
#define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
| (extract32(inst, 25, 6) << 5) \
| (extract32(inst, 7, 1) << 11) \
| (sextract64(inst, 31, 1) << 12))
#define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
| (sextract64(inst, 25, 7) << 5))
#define GET_JAL_IMM(inst) ((extract32(inst, 21, 10) << 1) \
| (extract32(inst, 20, 1) << 11) \
| (extract32(inst, 12, 8) << 12) \
| (sextract64(inst, 31, 1) << 20))
#define GET_RM(inst) extract32(inst, 12, 3)
#define GET_RS3(inst) extract32(inst, 27, 5)
#define GET_RS1(inst) extract32(inst, 15, 5)
#define GET_RS2(inst) extract32(inst, 20, 5)
#define GET_RD(inst) extract32(inst, 7, 5)
#define GET_IMM(inst) sextract64(inst, 20, 12)
/* RVC decoding macros */
#define GET_C_IMM(inst) (extract32(inst, 2, 5) \
| (sextract64(inst, 12, 1) << 5))
#define GET_C_ZIMM(inst) (extract32(inst, 2, 5) \
| (extract32(inst, 12, 1) << 5))
#define GET_C_ADDI4SPN_IMM(inst) ((extract32(inst, 6, 1) << 2) \
| (extract32(inst, 5, 1) << 3) \
| (extract32(inst, 11, 2) << 4) \
| (extract32(inst, 7, 4) << 6))
#define GET_C_ADDI16SP_IMM(inst) ((extract32(inst, 6, 1) << 4) \
| (extract32(inst, 2, 1) << 5) \
| (extract32(inst, 5, 1) << 6) \
| (extract32(inst, 3, 2) << 7) \
| (sextract64(inst, 12, 1) << 9))
#define GET_C_LWSP_IMM(inst) ((extract32(inst, 4, 3) << 2) \
| (extract32(inst, 12, 1) << 5) \
| (extract32(inst, 2, 2) << 6))
#define GET_C_LDSP_IMM(inst) ((extract32(inst, 5, 2) << 3) \
| (extract32(inst, 12, 1) << 5) \
| (extract32(inst, 2, 3) << 6))
#define GET_C_SWSP_IMM(inst) ((extract32(inst, 9, 4) << 2) \
| (extract32(inst, 7, 2) << 6))
#define GET_C_SDSP_IMM(inst) ((extract32(inst, 10, 3) << 3) \
| (extract32(inst, 7, 3) << 6))
#define GET_C_LW_IMM(inst) ((extract32(inst, 6, 1) << 2) \
| (extract32(inst, 10, 3) << 3) \
| (extract32(inst, 5, 1) << 6))
#define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \
| (extract16(inst, 5, 2) << 6))
#define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \
| (extract32(inst, 11, 1) << 4) \
| (extract32(inst, 2, 1) << 5) \
| (extract32(inst, 7, 1) << 6) \
| (extract32(inst, 6, 1) << 7) \
| (extract32(inst, 9, 2) << 8) \
| (extract32(inst, 8, 1) << 10) \
| (sextract64(inst, 12, 1) << 11))
#define GET_C_B_IMM(inst) ((extract32(inst, 3, 2) << 1) \
| (extract32(inst, 10, 2) << 3) \
| (extract32(inst, 2, 1) << 5) \
| (extract32(inst, 5, 2) << 6) \
| (sextract64(inst, 12, 1) << 8))
#define GET_C_SIMM3(inst) extract32(inst, 10, 3)
#define GET_C_RD(inst) GET_RD(inst)
#define GET_C_RS1(inst) GET_RD(inst)
#define GET_C_RS2(inst) extract32(inst, 2, 5)
#define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3))
#define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3))
#endif

208
qemu/target/riscv/op_helper.c Normal file
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@@ -0,0 +1,208 @@
/*
* RISC-V Emulation Helpers for QEMU.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
/* Exceptions processing helpers */
void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc)
{
CPUState *cs = env_cpu(env);
qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
cs->exception_index = exception;
cpu_loop_exit_restore(cs, pc);
}
void helper_raise_exception(CPURISCVState *env, uint32_t exception)
{
riscv_raise_exception(env, exception, 0);
}
target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
target_ulong csr)
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
target_ulong prev_priv, prev_virt, mstatus;
if (!(env->priv >= PRV_S)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->sepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
mstatus = env->mstatus;
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
/* We support Hypervisor extensions and virtulisation is disabled */
target_ulong hstatus = env->hstatus;
prev_priv = get_field(mstatus, MSTATUS_SPP);
prev_virt = get_field(hstatus, HSTATUS_SPV);
hstatus = set_field(hstatus, HSTATUS_SPV,
get_field(hstatus, HSTATUS_SP2V));
mstatus = set_field(mstatus, MSTATUS_SPP,
get_field(hstatus, HSTATUS_SP2P));
hstatus = set_field(hstatus, HSTATUS_SP2V, 0);
hstatus = set_field(hstatus, HSTATUS_SP2P, 0);
mstatus = set_field(mstatus, SSTATUS_SIE,
get_field(mstatus, SSTATUS_SPIE));
mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
env->mstatus = mstatus;
env->hstatus = hstatus;
if (prev_virt) {
riscv_cpu_swap_hypervisor_regs(env);
}
riscv_cpu_set_virt_enabled(env, prev_virt);
} else {
prev_priv = get_field(mstatus, MSTATUS_SPP);
mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_SIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
env->mstatus = mstatus;
}
riscv_cpu_set_mode(env, prev_priv);
return retpc;
}
target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
if (!(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->mepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
#ifdef TARGET_RISCV32
env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0);
#else
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
#endif
env->mstatus = mstatus;
riscv_cpu_set_mode(env, prev_priv);
if (riscv_has_ext(env, RVH)) {
if (prev_virt) {
riscv_cpu_swap_hypervisor_regs(env);
}
riscv_cpu_set_virt_enabled(env, prev_virt);
}
return retpc;
}
void helper_wfi(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
if ((env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TW)) ||
riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
cs->exception_index = EXCP_HLT;
cpu_loop_exit(cs);
}
}
void helper_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
if (!(env->priv >= PRV_S) ||
(env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
tlb_flush(cs);
}
}
void helper_uc_riscv_exit(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
cs->exception_index = EXCP_HLT;
cs->halted = 1;
cpu_loop_exit(cs);
}

379
qemu/target/riscv/pmp.c Normal file
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/*
* QEMU RISC-V PMP (Physical Memory Protection)
*
* Author: Daire McNamara, daire.mcnamara@emdalo.com
* Ivan Griffin, ivan.griffin@emdalo.com
*
* This provides a RISC-V Physical Memory Protection implementation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
/*
* Accessor method to extract address matching type 'a field' from cfg reg
*/
static inline uint8_t pmp_get_a_field(uint8_t cfg)
{
uint8_t a = cfg >> 3;
return a & 0x3;
}
/*
* Check whether a PMP is locked or not.
*/
static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
{
if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
return 1;
}
/* Top PMP has no 'next' to check */
if ((pmp_index + 1u) >= MAX_RISCV_PMPS) {
return 0;
}
/* In TOR mode, need to check the lock bit of the next pmp
* (if there is a next)
*/
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
(PMP_AMATCH_TOR == a_field)) {
return 1;
}
return 0;
}
/*
* Count the number of active rules.
*/
static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
{
return env->pmp_state.num_rules;
}
/*
* Accessor to get the cfg reg for a specific PMP/HART
*/
static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
{
if (pmp_index < MAX_RISCV_PMPS) {
return env->pmp_state.pmp[pmp_index].cfg_reg;
}
return 0;
}
/*
* Accessor to set the cfg reg for a specific PMP/HART
* Bounds checks and relevant lock bit.
*/
static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
{
if (pmp_index < MAX_RISCV_PMPS) {
if (!pmp_is_locked(env, pmp_index)) {
env->pmp_state.pmp[pmp_index].cfg_reg = val;
pmp_update_rule(env, pmp_index);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpcfg write - out of bounds\n");
}
}
static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
{
/*
aaaa...aaa0 8-byte NAPOT range
aaaa...aa01 16-byte NAPOT range
aaaa...a011 32-byte NAPOT range
...
aa01...1111 2^XLEN-byte NAPOT range
a011...1111 2^(XLEN+1)-byte NAPOT range
0111...1111 2^(XLEN+2)-byte NAPOT range
1111...1111 Reserved
*/
if (a == -1) {
*sa = 0u;
*ea = -1;
return;
} else {
target_ulong t1 = ctz64(~a);
target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2;
target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1;
*sa = base;
*ea = base + range;
}
}
/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
* end address values.
* This function is called relatively infrequently whereas the check that
* an address is within a pmp rule is called often, so optimise that one
*/
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
{
int i;
env->pmp_state.num_rules = 0;
uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
target_ulong prev_addr = 0u;
target_ulong sa = 0u;
target_ulong ea = 0u;
if (pmp_index >= 1u) {
prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg;
}
switch (pmp_get_a_field(this_cfg)) {
case PMP_AMATCH_OFF:
sa = 0u;
ea = -1;
break;
case PMP_AMATCH_TOR:
sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
ea = (this_addr << 2) - 1u;
break;
case PMP_AMATCH_NA4:
sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
ea = (this_addr + 4u) - 1u;
break;
case PMP_AMATCH_NAPOT:
pmp_decode_napot(this_addr, &sa, &ea);
break;
default:
sa = 0u;
ea = 0u;
break;
}
env->pmp_state.addr[pmp_index].sa = sa;
env->pmp_state.addr[pmp_index].ea = ea;
for (i = 0; i < MAX_RISCV_PMPS; i++) {
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
if (PMP_AMATCH_OFF != a_field) {
env->pmp_state.num_rules++;
}
}
}
static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
{
int result = 0;
if ((addr >= env->pmp_state.addr[pmp_index].sa)
&& (addr <= env->pmp_state.addr[pmp_index].ea)) {
result = 1;
} else {
result = 0;
}
return result;
}
/*
* Public Interface
*/
/*
* Check if the address has required RWX privs to complete desired operation
*/
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t privs, target_ulong mode)
{
int i = 0;
int ret = -1;
int pmp_size = 0;
target_ulong s = 0;
target_ulong e = 0;
pmp_priv_t allowed_privs = 0;
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
return true;
}
/*
* if size is unknown (0), assume that all bytes
* from addr to the end of the page will be accessed.
*/
if (size == 0) {
#ifdef _MSC_VER
pmp_size = 0 - (addr | TARGET_PAGE_MASK);
#else
pmp_size = -(addr | TARGET_PAGE_MASK);
#endif
} else {
pmp_size = size;
}
/* 1.10 draft priv spec states there is an implicit order
from low to high */
for (i = 0; i < MAX_RISCV_PMPS; i++) {
s = pmp_is_in_range(env, i, addr);
e = pmp_is_in_range(env, i, addr + pmp_size - 1);
/* partially inside */
if ((s + e) == 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"pmp violation - access is partially inside\n");
ret = 0;
break;
}
/* fully inside */
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
/*
* If the PMP entry is not off and the address is in range, do the priv
* check
*/
if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
if ((mode != PRV_M) || pmp_is_locked(env, i)) {
allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
}
if ((privs & allowed_privs) == privs) {
ret = 1;
break;
} else {
ret = 0;
break;
}
}
}
/* No rule matched */
if (ret == -1) {
if (mode == PRV_M) {
ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
* M-Mode access, the access succeeds */
} else {
ret = 0; /* Other modes are not allowed to succeed if they don't
* match a rule, but there are rules. We've checked for
* no rule earlier in this function. */
}
}
return ret == 1 ? true : false;
}
/*
* Handle a write to a pmpcfg CSP
*/
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
target_ulong val)
{
int i;
uint8_t cfg_val;
if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpcfg write - incorrect address\n");
return;
}
for (i = 0; i < sizeof(target_ulong); i++) {
cfg_val = (val >> 8 * i) & 0xff;
pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
cfg_val);
}
}
/*
* Handle a read from a pmpcfg CSP
*/
target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
{
int i;
target_ulong cfg_val = 0;
target_ulong val = 0;
for (i = 0; i < sizeof(target_ulong); i++) {
val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
cfg_val |= (val << (i * 8));
}
return cfg_val;
}
/*
* Handle a write to a pmpaddr CSP
*/
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val)
{
if (addr_index < MAX_RISCV_PMPS) {
if (!pmp_is_locked(env, addr_index)) {
env->pmp_state.pmp[addr_index].addr_reg = val;
pmp_update_rule(env, addr_index);
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - out of bounds\n");
}
}
/*
* Handle a read from a pmpaddr CSP
*/
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
{
target_ulong val = 0;
if (addr_index < MAX_RISCV_PMPS) {
val = env->pmp_state.pmp[addr_index].addr_reg;
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr read - out of bounds\n");
}
return val;
}

64
qemu/target/riscv/pmp.h Normal file
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@@ -0,0 +1,64 @@
/*
* QEMU RISC-V PMP (Physical Memory Protection)
*
* Author: Daire McNamara, daire.mcnamara@emdalo.com
* Ivan Griffin, ivan.griffin@emdalo.com
*
* This provides a RISC-V Physical Memory Protection interface
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef RISCV_PMP_H
#define RISCV_PMP_H
typedef enum {
PMP_READ = 1 << 0,
PMP_WRITE = 1 << 1,
PMP_EXEC = 1 << 2,
PMP_LOCK = 1 << 7
} pmp_priv_t;
typedef enum {
PMP_AMATCH_OFF, /* Null (off) */
PMP_AMATCH_TOR, /* Top of Range */
PMP_AMATCH_NA4, /* Naturally aligned four-byte region */
PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
} pmp_am_t;
typedef struct {
target_ulong addr_reg;
uint8_t cfg_reg;
} pmp_entry_t;
typedef struct {
target_ulong sa;
target_ulong ea;
} pmp_addr_t;
typedef struct {
pmp_entry_t pmp[MAX_RISCV_PMPS];
pmp_addr_t addr[MAX_RISCV_PMPS];
uint32_t num_rules;
} pmp_table_t;
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
target_ulong val);
target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val);
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t priv, target_ulong mode);
#endif

477
qemu/target/riscv/riscv32/decode_insn16.inc.c Normal file
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@@ -0,0 +1,477 @@
/* This file is autogenerated by scripts/decodetree.py. */
#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
# pragma GCC diagnostic push
# pragma GCC diagnostic ignored "-Wredundant-decls"
# ifdef __clang__
# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
# endif
#endif
typedef arg_empty arg_illegal;
static bool trans_illegal(DisasContext *ctx, arg_illegal *a);
typedef arg_i arg_addi;
static bool trans_addi(DisasContext *ctx, arg_addi *a);
typedef arg_i arg_fld;
static bool trans_fld(DisasContext *ctx, arg_fld *a);
typedef arg_i arg_lw;
static bool trans_lw(DisasContext *ctx, arg_lw *a);
typedef arg_s arg_fsd;
static bool trans_fsd(DisasContext *ctx, arg_fsd *a);
typedef arg_s arg_sw;
static bool trans_sw(DisasContext *ctx, arg_sw *a);
typedef arg_u arg_lui;
static bool trans_lui(DisasContext *ctx, arg_lui *a);
typedef arg_shift arg_srli;
static bool trans_srli(DisasContext *ctx, arg_srli *a);
typedef arg_shift arg_srai;
static bool trans_srai(DisasContext *ctx, arg_srai *a);
typedef arg_i arg_andi;
static bool trans_andi(DisasContext *ctx, arg_andi *a);
typedef arg_r arg_sub;
static bool trans_sub(DisasContext *ctx, arg_sub *a);
typedef arg_r arg_xor;
static bool trans_xor(DisasContext *ctx, arg_xor *a);
typedef arg_r arg_or;
static bool trans_or(DisasContext *ctx, arg_or *a);
typedef arg_r arg_and;
static bool trans_and(DisasContext *ctx, arg_and *a);
typedef arg_j arg_jal;
static bool trans_jal(DisasContext *ctx, arg_jal *a);
typedef arg_b arg_beq;
static bool trans_beq(DisasContext *ctx, arg_beq *a);
typedef arg_b arg_bne;
static bool trans_bne(DisasContext *ctx, arg_bne *a);
typedef arg_shift arg_slli;
static bool trans_slli(DisasContext *ctx, arg_slli *a);
typedef arg_i arg_jalr;
static bool trans_jalr(DisasContext *ctx, arg_jalr *a);
typedef arg_empty arg_ebreak;
static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a);
typedef arg_r arg_add;
static bool trans_add(DisasContext *ctx, arg_add *a);
typedef arg_i arg_flw;
static bool trans_flw(DisasContext *ctx, arg_flw *a);
typedef arg_s arg_fsw;
static bool trans_fsw(DisasContext *ctx, arg_fsw *a);
#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
# pragma GCC diagnostic pop
#endif
static void decode_insn16_extract_c_addi16sp(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_4(ctx, deposit32(deposit32(deposit32(deposit32(extract32(insn, 6, 1), 1, 31, extract32(insn, 2, 1)), 2, 30, extract32(insn, 5, 1)), 3, 29, extract32(insn, 3, 2)), 5, 27, sextract32(insn, 12, 1)));
a->rs1 = 2;
a->rd = 2;
}
static void decode_insn16_extract_c_addi4spn(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(deposit32(deposit32(extract32(insn, 6, 1), 1, 31, extract32(insn, 5, 1)), 2, 30, extract32(insn, 11, 2)), 4, 28, extract32(insn, 7, 4)));
a->rs1 = 2;
a->rd = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_c_andi(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = deposit32(extract32(insn, 2, 5), 5, 27, sextract32(insn, 12, 1));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rd = ex_rvc_register(ctx, extract32(insn, 7, 3));
}
static void decode_insn16_extract_c_jalr(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = 0;
a->rs1 = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_ldsp(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_3(ctx, deposit32(deposit32(extract32(insn, 5, 2), 2, 30, extract32(insn, 12, 1)), 3, 29, extract32(insn, 2, 3)));
a->rs1 = 2;
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_li(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = deposit32(extract32(insn, 2, 5), 5, 27, sextract32(insn, 12, 1));
a->rs1 = 0;
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_lui(DisasContext *ctx, arg_u *a, uint16_t insn)
{
a->imm = ex_shift_12(ctx, deposit32(extract32(insn, 2, 5), 5, 27, sextract32(insn, 12, 1)));
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_lwsp(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(deposit32(extract32(insn, 4, 3), 3, 29, extract32(insn, 12, 1)), 4, 28, extract32(insn, 2, 2)));
a->rs1 = 2;
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_mv(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = 0;
a->rs1 = extract32(insn, 2, 5);
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_sdsp(DisasContext *ctx, arg_s *a, uint16_t insn)
{
a->imm = ex_shift_3(ctx, deposit32(extract32(insn, 10, 3), 3, 29, extract32(insn, 7, 3)));
a->rs1 = 2;
a->rs2 = extract32(insn, 2, 5);
}
static void decode_insn16_extract_c_shift(DisasContext *ctx, arg_shift *a, uint16_t insn)
{
a->rd = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->shamt = ex_rvc_shifti(ctx, deposit32(extract32(insn, 2, 5), 5, 27, extract32(insn, 12, 1)));
}
static void decode_insn16_extract_c_shift2(DisasContext *ctx, arg_shift *a, uint16_t insn)
{
a->rd = extract32(insn, 7, 5);
a->rs1 = extract32(insn, 7, 5);
a->shamt = ex_rvc_shifti(ctx, deposit32(extract32(insn, 2, 5), 5, 27, extract32(insn, 12, 1)));
}
static void decode_insn16_extract_c_swsp(DisasContext *ctx, arg_s *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(extract32(insn, 9, 4), 4, 28, extract32(insn, 7, 2)));
a->rs1 = 2;
a->rs2 = extract32(insn, 2, 5);
}
static void decode_insn16_extract_cb_z(DisasContext *ctx, arg_b *a, uint16_t insn)
{
a->imm = ex_shift_1(ctx, deposit32(deposit32(deposit32(deposit32(extract32(insn, 3, 2), 2, 30, extract32(insn, 10, 2)), 4, 28, extract32(insn, 2, 1)), 5, 27, extract32(insn, 5, 2)), 7, 25, sextract32(insn, 12, 1)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rs2 = 0;
}
static void decode_insn16_extract_ci(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = deposit32(extract32(insn, 2, 5), 5, 27, sextract32(insn, 12, 1));
a->rs1 = extract32(insn, 7, 5);
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_cj(DisasContext *ctx, arg_j *a, uint16_t insn)
{
a->imm = ex_shift_1(ctx, deposit32(deposit32(deposit32(deposit32(deposit32(deposit32(deposit32(extract32(insn, 3, 3), 3, 29, extract32(insn, 11, 1)), 4, 28, extract32(insn, 2, 1)), 5, 27, extract32(insn, 7, 1)), 6, 26, extract32(insn, 6, 1)), 7, 25, extract32(insn, 9, 2)), 9, 23, extract32(insn, 8, 1)), 10, 22, sextract32(insn, 12, 1)));
}
static void decode_insn16_extract_cl_d(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_3(ctx, deposit32(extract32(insn, 10, 3), 3, 29, extract32(insn, 5, 2)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rd = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_cl_w(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(deposit32(extract32(insn, 6, 1), 1, 31, extract32(insn, 10, 3)), 4, 28, extract32(insn, 5, 1)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rd = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_cr(DisasContext *ctx, arg_r *a, uint16_t insn)
{
a->rs2 = extract32(insn, 2, 5);
a->rs1 = extract32(insn, 7, 5);
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_cs_2(DisasContext *ctx, arg_r *a, uint16_t insn)
{
a->rs2 = ex_rvc_register(ctx, extract32(insn, 2, 3));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rd = ex_rvc_register(ctx, extract32(insn, 7, 3));
}
static void decode_insn16_extract_cs_d(DisasContext *ctx, arg_s *a, uint16_t insn)
{
a->imm = ex_shift_3(ctx, deposit32(extract32(insn, 10, 3), 3, 29, extract32(insn, 5, 2)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rs2 = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_cs_w(DisasContext *ctx, arg_s *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(deposit32(extract32(insn, 6, 1), 1, 31, extract32(insn, 10, 3)), 4, 28, extract32(insn, 5, 1)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rs2 = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_decode_insn16_Fmt_22(DisasContext *ctx, arg_empty *a, uint16_t insn)
{
}
static bool decode_insn16(DisasContext *ctx, uint16_t insn)
{
union {
arg_b f_b;
arg_empty f_empty;
arg_i f_i;
arg_j f_j;
arg_r f_r;
arg_s f_s;
arg_shift f_shift;
arg_u f_u;
} u;
switch (insn & 0x0000e003) {
case 0x00000000:
/* 000..... ......00 */
if ((insn & 0x00001fe0) == 0x00000000) {
/* 00000000 000...00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:87 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
ctx->invalid = true;
if (trans_illegal(ctx, &u.f_empty)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:88 */
decode_insn16_extract_c_addi4spn(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
return false;
case 0x00000001:
/* 000..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:96 */
decode_insn16_extract_ci(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
return false;
case 0x00000002:
/* 000..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:115 */
decode_insn16_extract_c_shift2(ctx, &u.f_shift, insn);
if (trans_slli(ctx, &u.f_shift)) return true;
return false;
case 0x00002000:
/* 001..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:90 */
decode_insn16_extract_cl_d(ctx, &u.f_i, insn);
if (trans_fld(ctx, &u.f_i)) return true;
return false;
case 0x00002001:
/* 001..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-32.decode:24 */
decode_insn16_extract_cj(ctx, &u.f_j, insn);
u.f_j.rd = 1;
if (trans_jal(ctx, &u.f_j)) return true;
return false;
case 0x00002002:
/* 001..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:116 */
decode_insn16_extract_c_ldsp(ctx, &u.f_i, insn);
if (trans_fld(ctx, &u.f_i)) return true;
return false;
case 0x00004000:
/* 010..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:91 */
decode_insn16_extract_cl_w(ctx, &u.f_i, insn);
if (trans_lw(ctx, &u.f_i)) return true;
return false;
case 0x00004001:
/* 010..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:97 */
decode_insn16_extract_c_li(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
return false;
case 0x00004002:
/* 010..... ......10 */
if ((insn & 0x00000f80) == 0x00000000) {
/* 010.0000 0.....10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:118 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_illegal(ctx, &u.f_empty)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:119 */
decode_insn16_extract_c_lwsp(ctx, &u.f_i, insn);
if (trans_lw(ctx, &u.f_i)) return true;
return false;
case 0x00006000:
/* 011..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-32.decode:20 */
decode_insn16_extract_cl_w(ctx, &u.f_i, insn);
if (trans_flw(ctx, &u.f_i)) return true;
return false;
case 0x00006001:
/* 011..... ......01 */
if ((insn & 0x0000107c) == 0x00000000) {
/* 0110.... .0000001 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:99 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_illegal(ctx, &u.f_empty)) return true;
}
if ((insn & 0x00000f80) == 0x00000100) {
/* 011.0001 0.....01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:100 */
decode_insn16_extract_c_addi16sp(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:101 */
decode_insn16_extract_c_lui(ctx, &u.f_u, insn);
if (trans_lui(ctx, &u.f_u)) return true;
return false;
case 0x00006002:
/* 011..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-32.decode:27 */
decode_insn16_extract_c_lwsp(ctx, &u.f_i, insn);
if (trans_flw(ctx, &u.f_i)) return true;
return false;
case 0x00008001:
/* 100..... ......01 */
switch ((insn >> 10) & 0x3) {
case 0x0:
/* 100.00.. ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:103 */
decode_insn16_extract_c_shift(ctx, &u.f_shift, insn);
if (trans_srli(ctx, &u.f_shift)) return true;
return false;
case 0x1:
/* 100.01.. ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:104 */
decode_insn16_extract_c_shift(ctx, &u.f_shift, insn);
if (trans_srai(ctx, &u.f_shift)) return true;
return false;
case 0x2:
/* 100.10.. ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:105 */
decode_insn16_extract_c_andi(ctx, &u.f_i, insn);
if (trans_andi(ctx, &u.f_i)) return true;
return false;
case 0x3:
/* 100.11.. ......01 */
decode_insn16_extract_cs_2(ctx, &u.f_r, insn);
switch (insn & 0x00001060) {
case 0x00000000:
/* 100011.. .00...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:106 */
if (trans_sub(ctx, &u.f_r)) return true;
return false;
case 0x00000020:
/* 100011.. .01...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:107 */
if (trans_xor(ctx, &u.f_r)) return true;
return false;
case 0x00000040:
/* 100011.. .10...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:108 */
if (trans_or(ctx, &u.f_r)) return true;
return false;
case 0x00000060:
/* 100011.. .11...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:109 */
if (trans_and(ctx, &u.f_r)) return true;
return false;
}
return false;
}
return false;
case 0x00008002:
/* 100..... ......10 */
switch ((insn >> 12) & 0x1) {
case 0x0:
/* 1000.... ......10 */
if ((insn & 0x00000ffc) == 0x00000000) {
/* 10000000 00000010 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:122 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_illegal(ctx, &u.f_empty)) return true;
}
if ((insn & 0x0000007c) == 0x00000000) {
/* 1000.... .0000010 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:123 */
decode_insn16_extract_c_jalr(ctx, &u.f_i, insn);
u.f_i.rd = 0;
if (trans_jalr(ctx, &u.f_i)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:124 */
decode_insn16_extract_c_mv(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
return false;
case 0x1:
/* 1001.... ......10 */
if ((insn & 0x00000ffc) == 0x00000000) {
/* 10010000 00000010 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:127 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_ebreak(ctx, &u.f_empty)) return true;
}
if ((insn & 0x0000007c) == 0x00000000) {
/* 1001.... .0000010 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:128 */
decode_insn16_extract_c_jalr(ctx, &u.f_i, insn);
u.f_i.rd = 1;
if (trans_jalr(ctx, &u.f_i)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:129 */
decode_insn16_extract_cr(ctx, &u.f_r, insn);
if (trans_add(ctx, &u.f_r)) return true;
return false;
}
return false;
case 0x0000a000:
/* 101..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:92 */
decode_insn16_extract_cs_d(ctx, &u.f_s, insn);
if (trans_fsd(ctx, &u.f_s)) return true;
return false;
case 0x0000a001:
/* 101..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:110 */
decode_insn16_extract_cj(ctx, &u.f_j, insn);
u.f_j.rd = 0;
if (trans_jal(ctx, &u.f_j)) return true;
return false;
case 0x0000a002:
/* 101..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:131 */
decode_insn16_extract_c_sdsp(ctx, &u.f_s, insn);
if (trans_fsd(ctx, &u.f_s)) return true;
return false;
case 0x0000c000:
/* 110..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:93 */
decode_insn16_extract_cs_w(ctx, &u.f_s, insn);
if (trans_sw(ctx, &u.f_s)) return true;
return false;
case 0x0000c001:
/* 110..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:111 */
decode_insn16_extract_cb_z(ctx, &u.f_b, insn);
if (trans_beq(ctx, &u.f_b)) return true;
return false;
case 0x0000c002:
/* 110..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:132 */
decode_insn16_extract_c_swsp(ctx, &u.f_s, insn);
if (trans_sw(ctx, &u.f_s)) return true;
return false;
case 0x0000e000:
/* 111..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-32.decode:21 */
decode_insn16_extract_cs_w(ctx, &u.f_s, insn);
if (trans_fsw(ctx, &u.f_s)) return true;
return false;
case 0x0000e001:
/* 111..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:112 */
decode_insn16_extract_cb_z(ctx, &u.f_b, insn);
if (trans_bne(ctx, &u.f_b)) return true;
return false;
case 0x0000e002:
/* 111..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-32.decode:28 */
decode_insn16_extract_c_swsp(ctx, &u.f_s, insn);
if (trans_fsw(ctx, &u.f_s)) return true;
return false;
}
return false;
}

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/* This file is autogenerated by scripts/decodetree.py. */
#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
# pragma GCC diagnostic push
# pragma GCC diagnostic ignored "-Wredundant-decls"
# ifdef __clang__
# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
# endif
#endif
typedef arg_empty arg_illegal;
static bool trans_illegal(DisasContext *ctx, arg_illegal *a);
typedef arg_i arg_addi;
static bool trans_addi(DisasContext *ctx, arg_addi *a);
typedef arg_i arg_fld;
static bool trans_fld(DisasContext *ctx, arg_fld *a);
typedef arg_i arg_lw;
static bool trans_lw(DisasContext *ctx, arg_lw *a);
typedef arg_s arg_fsd;
static bool trans_fsd(DisasContext *ctx, arg_fsd *a);
typedef arg_s arg_sw;
static bool trans_sw(DisasContext *ctx, arg_sw *a);
typedef arg_u arg_lui;
static bool trans_lui(DisasContext *ctx, arg_lui *a);
typedef arg_shift arg_srli;
static bool trans_srli(DisasContext *ctx, arg_srli *a);
typedef arg_shift arg_srai;
static bool trans_srai(DisasContext *ctx, arg_srai *a);
typedef arg_i arg_andi;
static bool trans_andi(DisasContext *ctx, arg_andi *a);
typedef arg_r arg_sub;
static bool trans_sub(DisasContext *ctx, arg_sub *a);
typedef arg_r arg_xor;
static bool trans_xor(DisasContext *ctx, arg_xor *a);
typedef arg_r arg_or;
static bool trans_or(DisasContext *ctx, arg_or *a);
typedef arg_r arg_and;
static bool trans_and(DisasContext *ctx, arg_and *a);
typedef arg_j arg_jal;
static bool trans_jal(DisasContext *ctx, arg_jal *a);
typedef arg_b arg_beq;
static bool trans_beq(DisasContext *ctx, arg_beq *a);
typedef arg_b arg_bne;
static bool trans_bne(DisasContext *ctx, arg_bne *a);
typedef arg_shift arg_slli;
static bool trans_slli(DisasContext *ctx, arg_slli *a);
typedef arg_i arg_jalr;
static bool trans_jalr(DisasContext *ctx, arg_jalr *a);
typedef arg_empty arg_ebreak;
static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a);
typedef arg_r arg_add;
static bool trans_add(DisasContext *ctx, arg_add *a);
typedef arg_i arg_ld;
static bool trans_ld(DisasContext *ctx, arg_ld *a);
typedef arg_s arg_sd;
static bool trans_sd(DisasContext *ctx, arg_sd *a);
typedef arg_i arg_addiw;
static bool trans_addiw(DisasContext *ctx, arg_addiw *a);
typedef arg_r arg_subw;
static bool trans_subw(DisasContext *ctx, arg_subw *a);
typedef arg_r arg_addw;
static bool trans_addw(DisasContext *ctx, arg_addw *a);
#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
# pragma GCC diagnostic pop
#endif
static void decode_insn16_extract_c_addi16sp(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_4(ctx, deposit32(deposit32(deposit32(deposit32(extract32(insn, 6, 1), 1, 31, extract32(insn, 2, 1)), 2, 30, extract32(insn, 5, 1)), 3, 29, extract32(insn, 3, 2)), 5, 27, sextract32(insn, 12, 1)));
a->rs1 = 2;
a->rd = 2;
}
static void decode_insn16_extract_c_addi4spn(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(deposit32(deposit32(extract32(insn, 6, 1), 1, 31, extract32(insn, 5, 1)), 2, 30, extract32(insn, 11, 2)), 4, 28, extract32(insn, 7, 4)));
a->rs1 = 2;
a->rd = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_c_andi(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = deposit32(extract32(insn, 2, 5), 5, 27, sextract32(insn, 12, 1));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rd = ex_rvc_register(ctx, extract32(insn, 7, 3));
}
static void decode_insn16_extract_c_jalr(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = 0;
a->rs1 = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_ldsp(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_3(ctx, deposit32(deposit32(extract32(insn, 5, 2), 2, 30, extract32(insn, 12, 1)), 3, 29, extract32(insn, 2, 3)));
a->rs1 = 2;
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_li(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = deposit32(extract32(insn, 2, 5), 5, 27, sextract32(insn, 12, 1));
a->rs1 = 0;
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_lui(DisasContext *ctx, arg_u *a, uint16_t insn)
{
a->imm = ex_shift_12(ctx, deposit32(extract32(insn, 2, 5), 5, 27, sextract32(insn, 12, 1)));
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_lwsp(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(deposit32(extract32(insn, 4, 3), 3, 29, extract32(insn, 12, 1)), 4, 28, extract32(insn, 2, 2)));
a->rs1 = 2;
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_mv(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = 0;
a->rs1 = extract32(insn, 2, 5);
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_c_sdsp(DisasContext *ctx, arg_s *a, uint16_t insn)
{
a->imm = ex_shift_3(ctx, deposit32(extract32(insn, 10, 3), 3, 29, extract32(insn, 7, 3)));
a->rs1 = 2;
a->rs2 = extract32(insn, 2, 5);
}
static void decode_insn16_extract_c_shift(DisasContext *ctx, arg_shift *a, uint16_t insn)
{
a->rd = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->shamt = ex_rvc_shifti(ctx, deposit32(extract32(insn, 2, 5), 5, 27, extract32(insn, 12, 1)));
}
static void decode_insn16_extract_c_shift2(DisasContext *ctx, arg_shift *a, uint16_t insn)
{
a->rd = extract32(insn, 7, 5);
a->rs1 = extract32(insn, 7, 5);
a->shamt = ex_rvc_shifti(ctx, deposit32(extract32(insn, 2, 5), 5, 27, extract32(insn, 12, 1)));
}
static void decode_insn16_extract_c_swsp(DisasContext *ctx, arg_s *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(extract32(insn, 9, 4), 4, 28, extract32(insn, 7, 2)));
a->rs1 = 2;
a->rs2 = extract32(insn, 2, 5);
}
static void decode_insn16_extract_cb_z(DisasContext *ctx, arg_b *a, uint16_t insn)
{
a->imm = ex_shift_1(ctx, deposit32(deposit32(deposit32(deposit32(extract32(insn, 3, 2), 2, 30, extract32(insn, 10, 2)), 4, 28, extract32(insn, 2, 1)), 5, 27, extract32(insn, 5, 2)), 7, 25, sextract32(insn, 12, 1)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rs2 = 0;
}
static void decode_insn16_extract_ci(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = deposit32(extract32(insn, 2, 5), 5, 27, sextract32(insn, 12, 1));
a->rs1 = extract32(insn, 7, 5);
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_cj(DisasContext *ctx, arg_j *a, uint16_t insn)
{
a->imm = ex_shift_1(ctx, deposit32(deposit32(deposit32(deposit32(deposit32(deposit32(deposit32(extract32(insn, 3, 3), 3, 29, extract32(insn, 11, 1)), 4, 28, extract32(insn, 2, 1)), 5, 27, extract32(insn, 7, 1)), 6, 26, extract32(insn, 6, 1)), 7, 25, extract32(insn, 9, 2)), 9, 23, extract32(insn, 8, 1)), 10, 22, sextract32(insn, 12, 1)));
}
static void decode_insn16_extract_cl_d(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_3(ctx, deposit32(extract32(insn, 10, 3), 3, 29, extract32(insn, 5, 2)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rd = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_cl_w(DisasContext *ctx, arg_i *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(deposit32(extract32(insn, 6, 1), 1, 31, extract32(insn, 10, 3)), 4, 28, extract32(insn, 5, 1)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rd = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_cr(DisasContext *ctx, arg_r *a, uint16_t insn)
{
a->rs2 = extract32(insn, 2, 5);
a->rs1 = extract32(insn, 7, 5);
a->rd = extract32(insn, 7, 5);
}
static void decode_insn16_extract_cs_2(DisasContext *ctx, arg_r *a, uint16_t insn)
{
a->rs2 = ex_rvc_register(ctx, extract32(insn, 2, 3));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rd = ex_rvc_register(ctx, extract32(insn, 7, 3));
}
static void decode_insn16_extract_cs_d(DisasContext *ctx, arg_s *a, uint16_t insn)
{
a->imm = ex_shift_3(ctx, deposit32(extract32(insn, 10, 3), 3, 29, extract32(insn, 5, 2)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rs2 = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_cs_w(DisasContext *ctx, arg_s *a, uint16_t insn)
{
a->imm = ex_shift_2(ctx, deposit32(deposit32(extract32(insn, 6, 1), 1, 31, extract32(insn, 10, 3)), 4, 28, extract32(insn, 5, 1)));
a->rs1 = ex_rvc_register(ctx, extract32(insn, 7, 3));
a->rs2 = ex_rvc_register(ctx, extract32(insn, 2, 3));
}
static void decode_insn16_extract_decode_insn16_Fmt_22(DisasContext *ctx, arg_empty *a, uint16_t insn)
{
}
static bool decode_insn16(DisasContext *ctx, uint16_t insn)
{
union {
arg_b f_b;
arg_empty f_empty;
arg_i f_i;
arg_j f_j;
arg_r f_r;
arg_s f_s;
arg_shift f_shift;
arg_u f_u;
} u;
switch (insn & 0x0000e003) {
case 0x00000000:
/* 000..... ......00 */
if ((insn & 0x00001fe0) == 0x00000000) {
/* 00000000 000...00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:87 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
ctx->invalid = true;
if (trans_illegal(ctx, &u.f_empty)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:88 */
decode_insn16_extract_c_addi4spn(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
return false;
case 0x00000001:
/* 000..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:96 */
decode_insn16_extract_ci(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
return false;
case 0x00000002:
/* 000..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:115 */
decode_insn16_extract_c_shift2(ctx, &u.f_shift, insn);
if (trans_slli(ctx, &u.f_shift)) return true;
return false;
case 0x00002000:
/* 001..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:90 */
decode_insn16_extract_cl_d(ctx, &u.f_i, insn);
if (trans_fld(ctx, &u.f_i)) return true;
return false;
case 0x00002001:
/* 001..... ......01 */
if ((insn & 0x00000f80) == 0x00000000) {
/* 001.0000 0.....01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-64.decode:25 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_illegal(ctx, &u.f_empty)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-64.decode:26 */
decode_insn16_extract_ci(ctx, &u.f_i, insn);
if (trans_addiw(ctx, &u.f_i)) return true;
return false;
case 0x00002002:
/* 001..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:116 */
decode_insn16_extract_c_ldsp(ctx, &u.f_i, insn);
if (trans_fld(ctx, &u.f_i)) return true;
return false;
case 0x00004000:
/* 010..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:91 */
decode_insn16_extract_cl_w(ctx, &u.f_i, insn);
if (trans_lw(ctx, &u.f_i)) return true;
return false;
case 0x00004001:
/* 010..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:97 */
decode_insn16_extract_c_li(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
return false;
case 0x00004002:
/* 010..... ......10 */
if ((insn & 0x00000f80) == 0x00000000) {
/* 010.0000 0.....10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:118 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_illegal(ctx, &u.f_empty)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:119 */
decode_insn16_extract_c_lwsp(ctx, &u.f_i, insn);
if (trans_lw(ctx, &u.f_i)) return true;
return false;
case 0x00006000:
/* 011..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-64.decode:20 */
decode_insn16_extract_cl_d(ctx, &u.f_i, insn);
if (trans_ld(ctx, &u.f_i)) return true;
return false;
case 0x00006001:
/* 011..... ......01 */
if ((insn & 0x0000107c) == 0x00000000) {
/* 0110.... .0000001 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:99 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_illegal(ctx, &u.f_empty)) return true;
}
if ((insn & 0x00000f80) == 0x00000100) {
/* 011.0001 0.....01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:100 */
decode_insn16_extract_c_addi16sp(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:101 */
decode_insn16_extract_c_lui(ctx, &u.f_u, insn);
if (trans_lui(ctx, &u.f_u)) return true;
return false;
case 0x00006002:
/* 011..... ......10 */
if ((insn & 0x00000f80) == 0x00000000) {
/* 011.0000 0.....10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-64.decode:33 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_illegal(ctx, &u.f_empty)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-64.decode:34 */
decode_insn16_extract_c_ldsp(ctx, &u.f_i, insn);
if (trans_ld(ctx, &u.f_i)) return true;
return false;
case 0x00008001:
/* 100..... ......01 */
switch ((insn >> 10) & 0x3) {
case 0x0:
/* 100.00.. ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:103 */
decode_insn16_extract_c_shift(ctx, &u.f_shift, insn);
if (trans_srli(ctx, &u.f_shift)) return true;
return false;
case 0x1:
/* 100.01.. ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:104 */
decode_insn16_extract_c_shift(ctx, &u.f_shift, insn);
if (trans_srai(ctx, &u.f_shift)) return true;
return false;
case 0x2:
/* 100.10.. ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:105 */
decode_insn16_extract_c_andi(ctx, &u.f_i, insn);
if (trans_andi(ctx, &u.f_i)) return true;
return false;
case 0x3:
/* 100.11.. ......01 */
decode_insn16_extract_cs_2(ctx, &u.f_r, insn);
switch (insn & 0x00001060) {
case 0x00000000:
/* 100011.. .00...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:106 */
if (trans_sub(ctx, &u.f_r)) return true;
return false;
case 0x00000020:
/* 100011.. .01...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:107 */
if (trans_xor(ctx, &u.f_r)) return true;
return false;
case 0x00000040:
/* 100011.. .10...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:108 */
if (trans_or(ctx, &u.f_r)) return true;
return false;
case 0x00000060:
/* 100011.. .11...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:109 */
if (trans_and(ctx, &u.f_r)) return true;
return false;
case 0x00001000:
/* 100111.. .00...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-64.decode:28 */
if (trans_subw(ctx, &u.f_r)) return true;
return false;
case 0x00001020:
/* 100111.. .01...01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-64.decode:29 */
if (trans_addw(ctx, &u.f_r)) return true;
return false;
}
return false;
}
return false;
case 0x00008002:
/* 100..... ......10 */
switch ((insn >> 12) & 0x1) {
case 0x0:
/* 1000.... ......10 */
if ((insn & 0x00000ffc) == 0x00000000) {
/* 10000000 00000010 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:122 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_illegal(ctx, &u.f_empty)) return true;
}
if ((insn & 0x0000007c) == 0x00000000) {
/* 1000.... .0000010 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:123 */
decode_insn16_extract_c_jalr(ctx, &u.f_i, insn);
u.f_i.rd = 0;
if (trans_jalr(ctx, &u.f_i)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:124 */
decode_insn16_extract_c_mv(ctx, &u.f_i, insn);
if (trans_addi(ctx, &u.f_i)) return true;
return false;
case 0x1:
/* 1001.... ......10 */
if ((insn & 0x00000ffc) == 0x00000000) {
/* 10010000 00000010 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:127 */
decode_insn16_extract_decode_insn16_Fmt_22(ctx, &u.f_empty, insn);
if (trans_ebreak(ctx, &u.f_empty)) return true;
}
if ((insn & 0x0000007c) == 0x00000000) {
/* 1001.... .0000010 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:128 */
decode_insn16_extract_c_jalr(ctx, &u.f_i, insn);
u.f_i.rd = 1;
if (trans_jalr(ctx, &u.f_i)) return true;
}
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:129 */
decode_insn16_extract_cr(ctx, &u.f_r, insn);
if (trans_add(ctx, &u.f_r)) return true;
return false;
}
return false;
case 0x0000a000:
/* 101..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:92 */
decode_insn16_extract_cs_d(ctx, &u.f_s, insn);
if (trans_fsd(ctx, &u.f_s)) return true;
return false;
case 0x0000a001:
/* 101..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:110 */
decode_insn16_extract_cj(ctx, &u.f_j, insn);
u.f_j.rd = 0;
if (trans_jal(ctx, &u.f_j)) return true;
return false;
case 0x0000a002:
/* 101..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:131 */
decode_insn16_extract_c_sdsp(ctx, &u.f_s, insn);
if (trans_fsd(ctx, &u.f_s)) return true;
return false;
case 0x0000c000:
/* 110..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:93 */
decode_insn16_extract_cs_w(ctx, &u.f_s, insn);
if (trans_sw(ctx, &u.f_s)) return true;
return false;
case 0x0000c001:
/* 110..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:111 */
decode_insn16_extract_cb_z(ctx, &u.f_b, insn);
if (trans_beq(ctx, &u.f_b)) return true;
return false;
case 0x0000c002:
/* 110..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:132 */
decode_insn16_extract_c_swsp(ctx, &u.f_s, insn);
if (trans_sw(ctx, &u.f_s)) return true;
return false;
case 0x0000e000:
/* 111..... ......00 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-64.decode:21 */
decode_insn16_extract_cs_d(ctx, &u.f_s, insn);
if (trans_sd(ctx, &u.f_s)) return true;
return false;
case 0x0000e001:
/* 111..... ......01 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16.decode:112 */
decode_insn16_extract_cb_z(ctx, &u.f_b, insn);
if (trans_bne(ctx, &u.f_b)) return true;
return false;
case 0x0000e002:
/* 111..... ......10 */
/* /home/me/projects/unicorn2/qemu-5.0.0-build/target/riscv/insn16-64.decode:36 */
decode_insn16_extract_c_sdsp(ctx, &u.f_s, insn);
if (trans_sd(ctx, &u.f_s)) return true;
return false;
}
return false;
}

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/*
* RISC-V emulation for qemu: main translation routines.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
#include "tcg/tcg-op.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/translator.h"
#include "instmap.h"
#include "unicorn/platform.h"
#include "uc_priv.h"
#include "exec/gen-icount.h"
/*
* Unicorn: Special disas state for exiting in the middle of tb.
*/
#define DISAS_UC_EXIT DISAS_TARGET_6
typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong priv_ver;
bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
no previous fp instruction. Note that we exit the TB when writing
to any system register, which includes CSR_FRM, so we do not have
to reset this known value. */
int frm;
bool ext_ifencei;
// Unicorn
struct uc_struct *uc;
bool invalid; // invalid instruction, discoverd by translator
} DisasContext;
#ifdef TARGET_RISCV64
/* convert riscv funct3 to qemu memop for load/store */
static const int tcg_memop_lookup[8] = {
// [0 ... 7] = -1,
[0] = MO_SB,
[1] = MO_TESW,
[2] = MO_TESL,
[3] = MO_TEQ,
[4] = MO_UB,
[5] = MO_TEUW,
[6] = MO_TEUL,
[7] = -1,
};
#endif
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
#else
#define CASE_OP_32_64(X) case X
#endif
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
{
return ctx->misa & ext;
}
static void generate_exception(DisasContext *ctx, int excp)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, ctx->base.pc_next);
TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, excp);
gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, helper_tmp);
tcg_temp_free_i32(tcg_ctx, helper_tmp);
ctx->base.is_jmp = DISAS_NORETURN;
}
static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, ctx->base.pc_next);
tcg_gen_st_tl(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->cpu_env, offsetof(CPURISCVState, badaddr));
TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, excp);
gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, helper_tmp);
tcg_temp_free_i32(tcg_ctx, helper_tmp);
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_exception_debug(TCGContext *tcg_ctx)
{
TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, EXCP_DEBUG);
gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, helper_tmp);
tcg_temp_free_i32(tcg_ctx, helper_tmp);
}
/* Wrapper around tcg_gen_exit_tb that handles single stepping */
static void exit_tb(DisasContext *ctx)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (ctx->base.singlestep_enabled) {
gen_exception_debug(tcg_ctx);
} else {
tcg_gen_exit_tb(tcg_ctx, NULL, 0);
}
}
/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
static void lookup_and_goto_ptr(DisasContext *ctx)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (ctx->base.singlestep_enabled) {
gen_exception_debug(tcg_ctx);
} else {
tcg_gen_lookup_and_goto_ptr(tcg_ctx);
}
}
static void gen_exception_illegal(DisasContext *ctx)
{
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
}
static void gen_exception_inst_addr_mis(DisasContext *ctx)
{
generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
}
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
{
if (unlikely(ctx->base.singlestep_enabled)) {
return false;
}
return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (use_goto_tb(ctx, dest)) {
/* chaining is only allowed when the jump is to the same page */
tcg_gen_goto_tb(tcg_ctx, n);
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, dest);
/* No need to check for single stepping here as use_goto_tb() will
* return false in case of single stepping.
*/
tcg_gen_exit_tb(tcg_ctx, ctx->base.tb, n);
} else {
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, dest);
lookup_and_goto_ptr(ctx);
}
}
/* Wrapper for getting reg values - need to check of reg is zero since
* cpu_gpr[0] is not actually allocated
*/
static inline void gen_get_gpr(TCGContext *tcg_ctx, TCGv t, int reg_num)
{
if (reg_num == 0) {
tcg_gen_movi_tl(tcg_ctx, t, 0);
} else {
tcg_gen_mov_tl(tcg_ctx, t, tcg_ctx->cpu_gpr[reg_num]);
}
}
/* Wrapper for setting reg values - need to check of reg is zero since
* cpu_gpr[0] is not actually allocated. this is more for safety purposes,
* since we usually avoid calling the OP_TYPE_gen function if we see a write to
* $zero
*/
static inline void gen_set_gpr(TCGContext *tcg_ctx, int reg_num_dst, TCGv t)
{
if (reg_num_dst != 0) {
tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[reg_num_dst], t);
}
}
static void gen_mulhsu(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv rl = tcg_temp_new(tcg_ctx);
TCGv rh = tcg_temp_new(tcg_ctx);
tcg_gen_mulu2_tl(tcg_ctx, rl, rh, arg1, arg2);
/* fix up for one negative */
tcg_gen_sari_tl(tcg_ctx, rl, arg1, TARGET_LONG_BITS - 1);
tcg_gen_and_tl(tcg_ctx, rl, rl, arg2);
tcg_gen_sub_tl(tcg_ctx, ret, rh, rl);
tcg_temp_free(tcg_ctx, rl);
tcg_temp_free(tcg_ctx, rh);
}
static void gen_div(TCGContext *tcg_ctx, TCGv ret, TCGv source1, TCGv source2)
{
TCGv cond1, cond2, zeroreg, resultopt1;
/*
* Handle by altering args to tcg_gen_div to produce req'd results:
* For overflow: want source1 in source1 and 1 in source2
* For div by zero: want -1 in source1 and 1 in source2 -> -1 result
*/
cond1 = tcg_temp_new(tcg_ctx);
cond2 = tcg_temp_new(tcg_ctx);
zeroreg = tcg_const_tl(tcg_ctx, 0);
resultopt1 = tcg_temp_new(tcg_ctx);
tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)-1);
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source1,
((target_ulong)1) << (TARGET_LONG_BITS - 1));
tcg_gen_and_tl(tcg_ctx, cond1, cond1, cond2); /* cond1 = overflow */
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
/* if div by zero, set source1 to -1, otherwise don't change */
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond2, zeroreg, source1,
resultopt1);
/* if overflow or div by zero, set source2 to 1, else don't change */
tcg_gen_or_tl(tcg_ctx, cond1, cond1, cond2);
tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1);
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2,
resultopt1);
tcg_gen_div_tl(tcg_ctx, ret, source1, source2);
tcg_temp_free(tcg_ctx, cond1);
tcg_temp_free(tcg_ctx, cond2);
tcg_temp_free(tcg_ctx, zeroreg);
tcg_temp_free(tcg_ctx, resultopt1);
}
static void gen_divu(TCGContext *tcg_ctx, TCGv ret, TCGv source1, TCGv source2)
{
TCGv cond1, zeroreg, resultopt1;
cond1 = tcg_temp_new(tcg_ctx);
zeroreg = tcg_const_tl(tcg_ctx, 0);
resultopt1 = tcg_temp_new(tcg_ctx);
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0);
tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)-1);
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond1, zeroreg, source1,
resultopt1);
tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1);
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2,
resultopt1);
tcg_gen_divu_tl(tcg_ctx, ret, source1, source2);
tcg_temp_free(tcg_ctx, cond1);
tcg_temp_free(tcg_ctx, zeroreg);
tcg_temp_free(tcg_ctx, resultopt1);
}
static void gen_rem(TCGContext *tcg_ctx, TCGv ret, TCGv source1, TCGv source2)
{
TCGv cond1, cond2, zeroreg, resultopt1;
cond1 = tcg_temp_new(tcg_ctx);
cond2 = tcg_temp_new(tcg_ctx);
zeroreg = tcg_const_tl(tcg_ctx, 0);
resultopt1 = tcg_temp_new(tcg_ctx);
tcg_gen_movi_tl(tcg_ctx, resultopt1, 1L);
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, (target_ulong)-1);
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source1,
(target_ulong)1 << (TARGET_LONG_BITS - 1));
tcg_gen_and_tl(tcg_ctx, cond2, cond1, cond2); /* cond1 = overflow */
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
/* if overflow or div by zero, set source2 to 1, else don't change */
tcg_gen_or_tl(tcg_ctx, cond2, cond1, cond2);
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond2, zeroreg, source2,
resultopt1);
tcg_gen_rem_tl(tcg_ctx, resultopt1, source1, source2);
/* if div by zero, just return the original dividend */
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
source1);
tcg_temp_free(tcg_ctx, cond1);
tcg_temp_free(tcg_ctx, cond2);
tcg_temp_free(tcg_ctx, zeroreg);
tcg_temp_free(tcg_ctx, resultopt1);
}
static void gen_remu(TCGContext *tcg_ctx, TCGv ret, TCGv source1, TCGv source2)
{
TCGv cond1, zeroreg, resultopt1;
cond1 = tcg_temp_new(tcg_ctx);
zeroreg = tcg_const_tl(tcg_ctx, 0);
resultopt1 = tcg_temp_new(tcg_ctx);
tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1);
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0);
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2,
resultopt1);
tcg_gen_remu_tl(tcg_ctx, resultopt1, source1, source2);
/* if div by zero, just return the original dividend */
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
source1);
tcg_temp_free(tcg_ctx, cond1);
tcg_temp_free(tcg_ctx, zeroreg);
tcg_temp_free(tcg_ctx, resultopt1);
}
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
target_ulong next_pc;
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
if (!has_ext(ctx, RVC)) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
}
}
if (rd != 0) {
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rd], ctx->pc_succ_insn);
}
gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
ctx->base.is_jmp = DISAS_NORETURN;
}
#ifdef TARGET_RISCV64
static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
TCGv t1 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, imm);
int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
if (memop < 0) {
gen_exception_illegal(ctx);
return;
}
tcg_gen_qemu_ld_tl(tcg_ctx, t1, t0, ctx->mem_idx, memop);
gen_set_gpr(tcg_ctx, rd, t1);
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
}
static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
TCGv dat = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, imm);
gen_get_gpr(tcg_ctx, dat, rs2);
int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
if (memop < 0) {
gen_exception_illegal(ctx);
return;
}
tcg_gen_qemu_st_tl(tcg_ctx, dat, t0, ctx->mem_idx, memop);
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, dat);
}
#endif
/* The states of mstatus_fs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
*/
static void mark_fs_dirty(DisasContext *ctx)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv tmp;
if (ctx->mstatus_fs == MSTATUS_FS) {
return;
}
/* Remember the state change for the rest of the TB. */
ctx->mstatus_fs = MSTATUS_FS;
tmp = tcg_temp_new(tcg_ctx);
tcg_gen_ld_tl(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tcg_ctx, tmp, tmp, MSTATUS_FS | MSTATUS_SD);
tcg_gen_st_tl(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) {
tcg_gen_ld_tl(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tcg_ctx, tmp, tmp, MSTATUS_FS | MSTATUS_SD);
tcg_gen_st_tl(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPURISCVState, mstatus_hs));
}
tcg_temp_free(tcg_ctx, tmp);
}
#if !defined(TARGET_RISCV64)
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0;
if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, imm);
switch (opc) {
case OPC_RISC_FLW:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
tcg_gen_qemu_ld_i64(tcg_ctx, tcg_ctx->cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
/* RISC-V requires NaN-boxing of narrower width floating point values */
tcg_gen_ori_i64(tcg_ctx, tcg_ctx->cpu_fpr[rd], tcg_ctx->cpu_fpr[rd], 0xffffffff00000000ULL);
break;
case OPC_RISC_FLD:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
tcg_gen_qemu_ld_i64(tcg_ctx, tcg_ctx->cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
}
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);
}
static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
int rs2, target_long imm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0;
if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, t0, rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, imm);
switch (opc) {
case OPC_RISC_FSW:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
tcg_gen_qemu_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
break;
case OPC_RISC_FSD:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
tcg_gen_qemu_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
}
tcg_temp_free(tcg_ctx, t0);
}
#endif
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv_i32 t0;
if (ctx->frm == rm) {
return;
}
ctx->frm = rm;
t0 = tcg_const_i32(tcg_ctx, rm);
gen_helper_set_rounding_mode(tcg_ctx, tcg_ctx->cpu_env, t0);
tcg_temp_free_i32(tcg_ctx, t0);
}
static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
{
uint8_t funct3 = extract16(opcode, 13, 3);
uint8_t rd_rs2 = GET_C_RS2S(opcode);
uint8_t rs1s = GET_C_RS1S(opcode);
switch (funct3) {
case 3:
#if defined(TARGET_RISCV64)
/* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
GET_C_LD_IMM(opcode));
#else
/* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
GET_C_LW_IMM(opcode));
#endif
break;
case 7:
#if defined(TARGET_RISCV64)
/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
GET_C_LD_IMM(opcode));
#else
/* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
GET_C_LW_IMM(opcode));
#endif
break;
}
}
static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
{
uint8_t op = extract16(opcode, 0, 2);
switch (op) {
case 0:
decode_RV32_64C0(ctx, opcode);
break;
}
}
#define EX_SH(amount) \
static int ex_shift_##amount(DisasContext *ctx, int imm) \
{ \
return imm << amount; \
}
EX_SH(1)
EX_SH(2)
EX_SH(3)
EX_SH(4)
EX_SH(12)
#define REQUIRE_EXT(ctx, ext) do { \
if (!has_ext(ctx, ext)) { \
return false; \
} \
} while (0)
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
}
static int ex_rvc_shifti(DisasContext *ctx, int imm)
{
/* For RV128 a shamt of 0 means a shift by 64. */
return imm ? imm : 64;
}
/* Include the auto-generated decoder for 32 bit insn */
#ifdef TARGET_RISCV32
#include "riscv32/decode_insn32.inc.c"
#else
#include "riscv64/decode_insn32.inc.c"
#endif
static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
void (*func)(TCGContext *, TCGv, TCGv, target_long))
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1;
source1 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
(*func)(tcg_ctx, source1, source1, a->imm);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
return true;
}
static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
void (*func)(TCGContext *, TCGv, TCGv, TCGv))
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1, source2;
source1 = tcg_temp_new(tcg_ctx);
source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
tcg_gen_movi_tl(tcg_ctx, source2, a->imm);
(*func)(tcg_ctx, source1, source1, source2);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
#ifdef TARGET_RISCV64
static void gen_addw(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_add_tl(tcg_ctx, ret, arg1, arg2);
tcg_gen_ext32s_tl(tcg_ctx, ret, ret);
}
static void gen_subw(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_sub_tl(tcg_ctx, ret, arg1, arg2);
tcg_gen_ext32s_tl(tcg_ctx, ret, ret);
}
static void gen_mulw(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_mul_tl(tcg_ctx, ret, arg1, arg2);
tcg_gen_ext32s_tl(tcg_ctx, ret, ret);
}
static bool gen_arith_div_w(TCGContext *tcg_ctx, arg_r *a,
void(*func)(TCGContext *, TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new(tcg_ctx);
source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
tcg_gen_ext32s_tl(tcg_ctx, source2, source2);
(*func)(tcg_ctx, source1, source1, source2);
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
static bool gen_arith_div_uw(TCGContext *tcg_ctx, arg_r *a,
void(*func)(TCGContext *, TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new(tcg_ctx);
source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
tcg_gen_ext32u_tl(tcg_ctx, source1, source1);
tcg_gen_ext32u_tl(tcg_ctx, source2, source2);
(*func)(tcg_ctx, source1, source1, source2);
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
#endif
static bool gen_arith(TCGContext *tcg_ctx, arg_r *a,
void(*func)(TCGContext *, TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new(tcg_ctx);
source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
(*func)(tcg_ctx, source1, source1, source2);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
static bool gen_shift(DisasContext *ctx, arg_r *a,
void(*func)(TCGContext *, TCGv, TCGv, TCGv))
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1 = tcg_temp_new(tcg_ctx);
TCGv source2 = tcg_temp_new(tcg_ctx);
gen_get_gpr(tcg_ctx, source1, a->rs1);
gen_get_gpr(tcg_ctx, source2, a->rs2);
tcg_gen_andi_tl(tcg_ctx, source2, source2, TARGET_LONG_BITS - 1);
(*func)(tcg_ctx, source1, source1, source2);
gen_set_gpr(tcg_ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
tcg_temp_free(tcg_ctx, source2);
return true;
}
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
/* Include the auto-generated decoder for 16 bit insn */
#ifdef TARGET_RISCV32
#include "riscv32/decode_insn16.inc.c"
#else
#include "riscv64/decode_insn16.inc.c"
#endif
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/* check for compressed insn */
if (extract16(opcode, 0, 2) != 3) {
if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->invalid = false;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (!decode_insn16(ctx, opcode)) {
/* fall back to old decoder */
decode_RV32_64C(ctx, opcode);
} else {
// invalid instruction does not advance PC
if (ctx->invalid) {
ctx->pc_succ_insn -= 2;
}
}
}
} else {
uint32_t opcode32 = opcode;
opcode32 = deposit32(opcode32, 16, 16,
translator_lduw(tcg_ctx, env, ctx->base.pc_next + 2));
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, opcode32)) {
ctx->pc_succ_insn = ctx->base.pc_next - 4;
gen_exception_illegal(ctx);
}
}
}
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cs->env_ptr;
RISCVCPU *cpu = RISCV_CPU(cs);
// unicorn setup
ctx->uc = cs->uc;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
if (riscv_has_ext(env, RVH)) {
ctx->virt_enabled = riscv_cpu_virt_enabled(env);
if (env->priv_ver == PRV_M &&
get_field(env->mstatus, MSTATUS_MPRV) &&
MSTATUS_MPV_ISSET(env)) {
ctx->virt_enabled = true;
} else if (env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
get_field(env->hstatus, HSTATUS_SPRV) &&
get_field(env->hstatus, HSTATUS_SPV)) {
ctx->virt_enabled = true;
}
} else {
ctx->virt_enabled = false;
}
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
}
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
{
}
static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_insn_start(tcg_ctx, ctx->base.pc_next);
}
static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
const CPUBreakpoint *bp)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, ctx->base.pc_next);
ctx->base.is_jmp = DISAS_NORETURN;
gen_exception_debug(tcg_ctx);
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
the logic setting tb->size below does the right thing. */
ctx->base.pc_next += 4;
return true;
}
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
struct uc_struct *uc = ctx->uc;
TCGContext *tcg_ctx = uc->tcg_ctx;
CPURISCVState *env = cpu->env_ptr;
uint16_t opcode16 = translator_lduw(tcg_ctx, env, ctx->base.pc_next);
TCGOp *tcg_op, *prev_op = NULL;
bool insn_hook = false;
// Unicorn: end address tells us to stop emulation
if (ctx->base.pc_next == ctx->uc->addr_end) {
// Unicorn: We have to exit current execution here.
dcbase->is_jmp = DISAS_UC_EXIT;
} else {
// Unicorn: trace this instruction on request
if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_CODE, ctx->base.pc_next)) {
// save the last operand
prev_op = tcg_last_op(tcg_ctx);
insn_hook = true;
gen_uc_tracecode(tcg_ctx, 4, UC_HOOK_CODE_IDX, uc, ctx->base.pc_next);
// the callback might want to stop emulation immediately
check_exit_request(tcg_ctx);
}
decode_opc(env, ctx, opcode16);
if (insn_hook) {
// Unicorn: patch the callback to have the proper instruction size.
if (prev_op) {
// As explained further up in the function where prev_op is
// assigned, we move forward in the tail queue, so we're modifying the
// move instruction generated by gen_uc_tracecode() that contains
// the instruction size to assign the proper size (replacing 0xF1F1F1F1).
tcg_op = QTAILQ_NEXT(prev_op, link);
} else {
// this instruction is the first emulated code ever,
// so the instruction operand is the first operand
tcg_op = QTAILQ_FIRST(&tcg_ctx->ops);
}
tcg_op->args[1] = ctx->pc_succ_insn - ctx->base.pc_next;
}
ctx->base.pc_next = ctx->pc_succ_insn;
if (ctx->base.is_jmp == DISAS_NEXT) {
target_ulong page_start;
page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
ctx->base.is_jmp = DISAS_TOO_MANY;
}
}
}
}
static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
switch (ctx->base.is_jmp) {
case DISAS_TOO_MANY:
gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
case DISAS_NORETURN:
break;
case DISAS_UC_EXIT:
gen_helper_uc_riscv_exit(ctx->uc->tcg_ctx, ctx->uc->tcg_ctx->cpu_env);
break;
default:
g_assert_not_reached();
}
}
static const TranslatorOps riscv_tr_ops = {
.init_disas_context = riscv_tr_init_disas_context,
.tb_start = riscv_tr_tb_start,
.insn_start = riscv_tr_insn_start,
.breakpoint_check = riscv_tr_breakpoint_check,
.translate_insn = riscv_tr_translate_insn,
.tb_stop = riscv_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
{
DisasContext ctx;
memset(&ctx, 0, sizeof(ctx));
translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
}
void riscv_translate_init(struct uc_struct *uc)
{
int i;
TCGContext *tcg_ctx = uc->tcg_ctx;
/* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
/* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
/* registers, unless you specifically block reads/writes to reg 0 */
tcg_ctx->cpu_gpr[0] = NULL;
for (i = 1; i < 32; i++) {
tcg_ctx->cpu_gpr[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
}
for (i = 0; i < 32; i++) {
tcg_ctx->cpu_fpr[i] = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env,
offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
}
tcg_ctx->cpu_pc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, pc), "pc");
tcg_ctx->load_res = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, load_res),
"load_res");
tcg_ctx->load_val = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
}

351
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/* Unicorn Emulator Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
#include "uc_priv.h"
#include "sysemu/cpus.h"
#include "cpu.h"
#include "unicorn_common.h"
#include "cpu_bits.h"
#include <unicorn/riscv.h>
#include "unicorn.h"
RISCVCPU *cpu_riscv_init(struct uc_struct *uc, const char *cpu_model);
static void riscv_set_pc(struct uc_struct *uc, uint64_t address)
{
RISCV_CPU(uc->cpu)->env.pc = address;
}
static void riscv_release(void *ctx)
{
int i;
TCGContext *tcg_ctx = (TCGContext *)ctx;
RISCVCPU *cpu = (RISCVCPU *)tcg_ctx->uc->cpu;
CPUTLBDesc *d = cpu->neg.tlb.d;
CPUTLBDescFast *f = cpu->neg.tlb.f;
CPUTLBDesc *desc;
CPUTLBDescFast *fast;
release_common(ctx);
for (i = 0; i < NB_MMU_MODES; i++) {
desc = &(d[i]);
fast = &(f[i]);
g_free(desc->iotlb);
g_free(fast->table);
}
}
void riscv_reg_reset(struct uc_struct *uc)
{
}
static void reg_read(CPURISCVState *env, unsigned int regid, void *value)
{
switch(regid) {
case UC_RISCV_REG_X0:
case UC_RISCV_REG_X1:
case UC_RISCV_REG_X2:
case UC_RISCV_REG_X3:
case UC_RISCV_REG_X4:
case UC_RISCV_REG_X5:
case UC_RISCV_REG_X6:
case UC_RISCV_REG_X7:
case UC_RISCV_REG_X8:
case UC_RISCV_REG_X9:
case UC_RISCV_REG_X10:
case UC_RISCV_REG_X11:
case UC_RISCV_REG_X12:
case UC_RISCV_REG_X13:
case UC_RISCV_REG_X14:
case UC_RISCV_REG_X15:
case UC_RISCV_REG_X16:
case UC_RISCV_REG_X17:
case UC_RISCV_REG_X18:
case UC_RISCV_REG_X19:
case UC_RISCV_REG_X20:
case UC_RISCV_REG_X21:
case UC_RISCV_REG_X22:
case UC_RISCV_REG_X23:
case UC_RISCV_REG_X24:
case UC_RISCV_REG_X25:
case UC_RISCV_REG_X26:
case UC_RISCV_REG_X27:
case UC_RISCV_REG_X28:
case UC_RISCV_REG_X29:
case UC_RISCV_REG_X30:
case UC_RISCV_REG_X31:
#ifdef TARGET_RISCV64
*(int64_t *)value = env->gpr[regid - UC_RISCV_REG_X0];
#else
*(int32_t *)value = env->gpr[regid - UC_RISCV_REG_X0];
#endif
break;
case UC_RISCV_REG_PC:
#ifdef TARGET_RISCV64
*(int64_t *)value = env->pc;
#else
*(int32_t *)value = env->pc;
#endif
break;
case UC_RISCV_REG_F0: // "ft0"
case UC_RISCV_REG_F1: // "ft1"
case UC_RISCV_REG_F2: // "ft2"
case UC_RISCV_REG_F3: // "ft3"
case UC_RISCV_REG_F4: // "ft4"
case UC_RISCV_REG_F5: // "ft5"
case UC_RISCV_REG_F6: // "ft6"
case UC_RISCV_REG_F7: // "ft7"
case UC_RISCV_REG_F8: // "fs0"
case UC_RISCV_REG_F9: // "fs1"
case UC_RISCV_REG_F10: // "fa0"
case UC_RISCV_REG_F11: // "fa1"
case UC_RISCV_REG_F12: // "fa2"
case UC_RISCV_REG_F13: // "fa3"
case UC_RISCV_REG_F14: // "fa4"
case UC_RISCV_REG_F15: // "fa5"
case UC_RISCV_REG_F16: // "fa6"
case UC_RISCV_REG_F17: // "fa7"
case UC_RISCV_REG_F18: // "fs2"
case UC_RISCV_REG_F19: // "fs3"
case UC_RISCV_REG_F20: // "fs4"
case UC_RISCV_REG_F21: // "fs5"
case UC_RISCV_REG_F22: // "fs6"
case UC_RISCV_REG_F23: // "fs7"
case UC_RISCV_REG_F24: // "fs8"
case UC_RISCV_REG_F25: // "fs9"
case UC_RISCV_REG_F26: // "fs10"
case UC_RISCV_REG_F27: // "fs11"
case UC_RISCV_REG_F28: // "ft8"
case UC_RISCV_REG_F29: // "ft9"
case UC_RISCV_REG_F30: // "ft10"
case UC_RISCV_REG_F31: // "ft11"
#ifdef TARGET_RISCV64
*(int64_t *)value = env->fpr[regid - UC_RISCV_REG_F0];
#else
*(int32_t *)value = env->fpr[regid - UC_RISCV_REG_F0];
#endif
break;
default:
break;
}
return;
}
static void reg_write(CPURISCVState *env, unsigned int regid, const void *value)
{
switch(regid) {
case UC_RISCV_REG_X0:
case UC_RISCV_REG_X1:
case UC_RISCV_REG_X2:
case UC_RISCV_REG_X3:
case UC_RISCV_REG_X4:
case UC_RISCV_REG_X5:
case UC_RISCV_REG_X6:
case UC_RISCV_REG_X7:
case UC_RISCV_REG_X8:
case UC_RISCV_REG_X9:
case UC_RISCV_REG_X10:
case UC_RISCV_REG_X11:
case UC_RISCV_REG_X12:
case UC_RISCV_REG_X13:
case UC_RISCV_REG_X14:
case UC_RISCV_REG_X15:
case UC_RISCV_REG_X16:
case UC_RISCV_REG_X17:
case UC_RISCV_REG_X18:
case UC_RISCV_REG_X19:
case UC_RISCV_REG_X20:
case UC_RISCV_REG_X21:
case UC_RISCV_REG_X22:
case UC_RISCV_REG_X23:
case UC_RISCV_REG_X24:
case UC_RISCV_REG_X25:
case UC_RISCV_REG_X26:
case UC_RISCV_REG_X27:
case UC_RISCV_REG_X28:
case UC_RISCV_REG_X29:
case UC_RISCV_REG_X30:
case UC_RISCV_REG_X31:
#ifdef TARGET_RISCV64
env->gpr[regid - UC_RISCV_REG_X0] = *(uint64_t *)value;
#else
env->gpr[regid - UC_RISCV_REG_X0] = *(uint32_t *)value;
#endif
break;
case UC_RISCV_REG_PC:
#ifdef TARGET_RISCV64
env->pc = *(uint64_t *)value;
#else
env->pc = *(uint32_t *)value;
#endif
break;
case UC_RISCV_REG_F0: // "ft0"
case UC_RISCV_REG_F1: // "ft1"
case UC_RISCV_REG_F2: // "ft2"
case UC_RISCV_REG_F3: // "ft3"
case UC_RISCV_REG_F4: // "ft4"
case UC_RISCV_REG_F5: // "ft5"
case UC_RISCV_REG_F6: // "ft6"
case UC_RISCV_REG_F7: // "ft7"
case UC_RISCV_REG_F8: // "fs0"
case UC_RISCV_REG_F9: // "fs1"
case UC_RISCV_REG_F10: // "fa0"
case UC_RISCV_REG_F11: // "fa1"
case UC_RISCV_REG_F12: // "fa2"
case UC_RISCV_REG_F13: // "fa3"
case UC_RISCV_REG_F14: // "fa4"
case UC_RISCV_REG_F15: // "fa5"
case UC_RISCV_REG_F16: // "fa6"
case UC_RISCV_REG_F17: // "fa7"
case UC_RISCV_REG_F18: // "fs2"
case UC_RISCV_REG_F19: // "fs3"
case UC_RISCV_REG_F20: // "fs4"
case UC_RISCV_REG_F21: // "fs5"
case UC_RISCV_REG_F22: // "fs6"
case UC_RISCV_REG_F23: // "fs7"
case UC_RISCV_REG_F24: // "fs8"
case UC_RISCV_REG_F25: // "fs9"
case UC_RISCV_REG_F26: // "fs10"
case UC_RISCV_REG_F27: // "fs11"
case UC_RISCV_REG_F28: // "ft8"
case UC_RISCV_REG_F29: // "ft9"
case UC_RISCV_REG_F30: // "ft10"
case UC_RISCV_REG_F31: // "ft11"
#ifdef TARGET_RISCV64
env->fpr[regid - UC_RISCV_REG_F0] = *(uint64_t *)value;
#else
env->fpr[regid - UC_RISCV_REG_F0] = *(uint32_t *)value;
#endif
break;
default:
break;
}
}
int riscv_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
{
CPURISCVState *env = &(RISCV_CPU(uc->cpu)->env);
int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
void *value = vals[i];
reg_read(env, regid, value);
}
return 0;
}
int riscv_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count)
{
CPURISCVState *env = &(RISCV_CPU(uc->cpu)->env);
int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
const void *value = vals[i];
reg_write(env, regid, value);
if(regid == UC_RISCV_REG_PC){
// force to quit execution and flush TB
uc->quit_request = true;
uc_emu_stop(uc);
}
}
return 0;
}
DEFAULT_VISIBILITY
#ifdef TARGET_RISCV32
int riscv32_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
#else
/* TARGET_RISCV64 */
int riscv64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
#endif
{
CPURISCVState *env = (CPURISCVState *)ctx->data;
int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
void *value = vals[i];
reg_read(env, regid, value);
}
return 0;
}
DEFAULT_VISIBILITY
#ifdef TARGET_RISCV32
int riscv32_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count)
#else
/* TARGET_RISCV64 */
int riscv64_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count)
#endif
{
CPURISCVState *env = (CPURISCVState *)ctx->data;
int i;
for (i = 0; i < count; i++) {
unsigned int regid = regs[i];
const void *value = vals[i];
reg_write(env, regid, value);
}
return 0;
}
static bool riscv_stop_interrupt(struct uc_struct *uc, int intno)
{
// detect stop exception
switch(intno){
default:
return false;
case RISCV_EXCP_UNICORN_END:
return true;
case RISCV_EXCP_BREAKPOINT:
uc->invalid_error = UC_ERR_EXCEPTION;
return true;
}
}
static bool riscv_insn_hook_validate(uint32_t insn_enum)
{
return false;
}
static int riscv_cpus_init(struct uc_struct *uc, const char *cpu_model)
{
RISCVCPU *cpu;
cpu = cpu_riscv_init(uc, cpu_model);
if (cpu == NULL) {
return -1;
}
return 0;
}
DEFAULT_VISIBILITY
#ifdef TARGET_RISCV32
void riscv32_uc_init(struct uc_struct* uc)
#else
/* TARGET_RISCV64 */
void riscv64_uc_init(struct uc_struct* uc)
#endif
{
uc->reg_read = riscv_reg_read;
uc->reg_write = riscv_reg_write;
uc->reg_reset = riscv_reg_reset;
uc->release = riscv_release;
uc->set_pc = riscv_set_pc;
uc->stop_interrupt = riscv_stop_interrupt;
uc->insn_hook_validate = riscv_insn_hook_validate;
uc->cpus_init = riscv_cpus_init;
uc->cpu_context_size = offsetof(CPURISCVState, rdtime_fn);
uc_common_init(uc);
}

21
qemu/target/riscv/unicorn.h Normal file
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/* Unicorn Emulator Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
#ifndef UC_QEMU_TARGET_RISCV_H
#define UC_QEMU_TARGET_RISCV_H
// functions to read & write registers
int riscv_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count);
int riscv_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count);
int riscv32_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count);
int riscv32_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count);
int riscv64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count);
int riscv64_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count);
void riscv_reg_reset(struct uc_struct *uc);
void riscv32_uc_init(struct uc_struct* uc);
void riscv64_uc_init(struct uc_struct* uc);
#endif