import Unicorn2
This commit is contained in:
Nguyen Anh Quynh
398
qemu/target/ppc/mmu-radix64.c
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398
qemu/target/ppc/mmu-radix64.c
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@@ -0,0 +1,398 @@
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/*
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* PowerPC Radix MMU mulation helpers for QEMU.
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*
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* Copyright (c) 2016 Suraj Jitindar Singh, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "mmu-radix64.h"
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#include "mmu-book3s-v3.h"
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static bool ppc_radix64_get_fully_qualified_addr(CPUPPCState *env, vaddr eaddr,
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uint64_t *lpid, uint64_t *pid)
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{
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if (msr_hv) { /* MSR[HV] -> Hypervisor/bare metal */
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switch (eaddr & R_EADDR_QUADRANT) {
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case R_EADDR_QUADRANT0:
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*lpid = 0;
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*pid = env->spr[SPR_BOOKS_PID];
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break;
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case R_EADDR_QUADRANT1:
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*lpid = env->spr[SPR_LPIDR];
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*pid = env->spr[SPR_BOOKS_PID];
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break;
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case R_EADDR_QUADRANT2:
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*lpid = env->spr[SPR_LPIDR];
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*pid = 0;
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break;
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case R_EADDR_QUADRANT3:
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*lpid = 0;
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*pid = 0;
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break;
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}
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} else { /* !MSR[HV] -> Guest */
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switch (eaddr & R_EADDR_QUADRANT) {
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case R_EADDR_QUADRANT0: /* Guest application */
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*lpid = env->spr[SPR_LPIDR];
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*pid = env->spr[SPR_BOOKS_PID];
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break;
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case R_EADDR_QUADRANT1: /* Illegal */
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case R_EADDR_QUADRANT2:
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return false;
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case R_EADDR_QUADRANT3: /* Guest OS */
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*lpid = env->spr[SPR_LPIDR];
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*pid = 0; /* pid set to 0 -> addresses guest operating system */
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break;
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}
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}
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return true;
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}
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static void ppc_radix64_raise_segi(PowerPCCPU *cpu, int rwx, vaddr eaddr)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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if (rwx == 2) { /* Instruction Segment Interrupt */
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cs->exception_index = POWERPC_EXCP_ISEG;
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} else { /* Data Segment Interrupt */
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cs->exception_index = POWERPC_EXCP_DSEG;
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env->spr[SPR_DAR] = eaddr;
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}
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env->error_code = 0;
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}
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static void ppc_radix64_raise_si(PowerPCCPU *cpu, int rwx, vaddr eaddr,
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uint32_t cause)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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if (rwx == 2) { /* Instruction Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_ISI;
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env->error_code = cause;
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} else { /* Data Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_DSI;
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if (rwx == 1) { /* Write -> Store */
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cause |= DSISR_ISSTORE;
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}
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env->spr[SPR_DSISR] = cause;
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env->spr[SPR_DAR] = eaddr;
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env->error_code = 0;
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}
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}
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static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
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int *fault_cause, int *prot)
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{
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CPUPPCState *env = &cpu->env;
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const int need_prot[] = { PAGE_READ, PAGE_WRITE, PAGE_EXEC };
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/* Check Page Attributes (pte58:59) */
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if (((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO) && (rwx == 2)) {
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/*
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* Radix PTE entries with the non-idempotent I/O attribute are treated
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* as guarded storage
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*/
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*fault_cause |= SRR1_NOEXEC_GUARD;
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return true;
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}
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/* Determine permissions allowed by Encoded Access Authority */
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if ((pte & R_PTE_EAA_PRIV) && msr_pr) { /* Insufficient Privilege */
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*prot = 0;
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} else if (msr_pr || (pte & R_PTE_EAA_PRIV)) {
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*prot = ppc_radix64_get_prot_eaa(pte);
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} else { /* !msr_pr && !(pte & R_PTE_EAA_PRIV) */
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*prot = ppc_radix64_get_prot_eaa(pte);
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*prot &= ppc_radix64_get_prot_amr(cpu); /* Least combined permissions */
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}
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/* Check if requested access type is allowed */
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if (need_prot[rwx] & ~(*prot)) { /* Page Protected for that Access */
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*fault_cause |= DSISR_PROTFAULT;
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return true;
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}
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return false;
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}
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static void ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte,
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hwaddr pte_addr, int *prot)
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{
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CPUState *cs = CPU(cpu);
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uint64_t npte;
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npte = pte | R_PTE_R; /* Always set reference bit */
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if (rwx == 1) { /* Store/Write */
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npte |= R_PTE_C; /* Set change bit */
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} else {
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/*
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* Treat the page as read-only for now, so that a later write
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* will pass through this function again to set the C bit.
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*/
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*prot &= ~PAGE_WRITE;
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}
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if (pte ^ npte) { /* If pte has changed then write it back */
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#ifdef UNICORN_ARCH_POSTFIX
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glue(stq_phys, UNICORN_ARCH_POSTFIX)(cs->uc, cs->as, pte_addr, npte);
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#else
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stq_phys(cs->uc, cs->as, pte_addr, npte);
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#endif
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}
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}
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static uint64_t ppc_radix64_walk_tree(PowerPCCPU *cpu, vaddr eaddr,
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uint64_t base_addr, uint64_t nls,
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hwaddr *raddr, int *psize,
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int *fault_cause, hwaddr *pte_addr)
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{
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CPUState *cs = CPU(cpu);
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uint64_t index, pde;
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if (nls < 5) { /* Directory maps less than 2**5 entries */
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*fault_cause |= DSISR_R_BADCONFIG;
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return 0;
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}
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/* Read page <directory/table> entry from guest address space */
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index = eaddr >> (*psize - nls); /* Shift */
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index &= ((1UL << nls) - 1); /* Mask */
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#ifdef UNICORN_ARCH_POSTFIX
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pde = glue(ldq_phys, UNICORN_ARCH_POSTFIX)(cs->uc, cs->as, base_addr + (index * sizeof(pde)));
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#else
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pde = ldq_phys(cs->uc, cs->as, base_addr + (index * sizeof(pde)));
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#endif
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if (!(pde & R_PTE_VALID)) { /* Invalid Entry */
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*fault_cause |= DSISR_NOPTE;
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return 0;
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}
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*psize -= nls;
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/* Check if Leaf Entry -> Page Table Entry -> Stop the Search */
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if (pde & R_PTE_LEAF) {
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uint64_t rpn = pde & R_PTE_RPN;
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uint64_t mask = (1UL << *psize) - 1;
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/* Or high bits of rpn and low bits to ea to form whole real addr */
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*raddr = (rpn & ~mask) | (eaddr & mask);
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*pte_addr = base_addr + (index * sizeof(pde));
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return pde;
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}
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/* Next Level of Radix Tree */
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return ppc_radix64_walk_tree(cpu, eaddr, pde & R_PDE_NLB, pde & R_PDE_NLS,
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raddr, psize, fault_cause, pte_addr);
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}
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static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
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{
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CPUPPCState *env = &cpu->env;
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if (!(pate->dw0 & PATE0_HR)) {
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return false;
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}
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if (lpid == 0 && !msr_hv) {
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return false;
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}
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/* More checks ... */
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return true;
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}
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int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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int mmu_idx)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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#if 0
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PPCVirtualHypervisorClass *vhc;
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#endif
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hwaddr raddr, pte_addr;
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uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
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int page_size, prot, fault_cause = 0;
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ppc_v3_pate_t pate;
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assert((rwx == 0) || (rwx == 1) || (rwx == 2));
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/* HV or virtual hypervisor Real Mode Access */
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if ((msr_hv) &&
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(((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0)))) {
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/* In real mode top 4 effective addr bits (mostly) ignored */
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raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
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/* In HV mode, add HRMOR if top EA bit is clear */
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if (msr_hv || !env->has_hv_mode) {
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if (!(eaddr >> 63)) {
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raddr |= env->spr[SPR_HRMOR];
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}
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}
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tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
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TARGET_PAGE_SIZE);
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return 0;
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}
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/*
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* Check UPRT (we avoid the check in real mode to deal with
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* transitional states during kexec.
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*/
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#if 0
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if (!ppc64_use_proc_tbl(cpu)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"LPCR:UPRT not set in radix mode ! LPCR="
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TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
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}
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#endif
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/* Virtual Mode Access - get the fully qualified address */
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if (!ppc_radix64_get_fully_qualified_addr(env, eaddr, &lpid, &pid)) {
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ppc_radix64_raise_segi(cpu, rwx, eaddr);
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return 1;
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}
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/* Get Process Table */
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#if 0
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if (cpu->vhyp) {
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vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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vhc->get_pate(cpu->vhyp, &pate);
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} else {
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#endif
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if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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return 1;
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}
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if (!validate_pate(cpu, lpid, &pate)) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
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}
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/* We don't support guest mode yet */
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if (lpid != 0) {
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fprintf(stderr, "PowerNV guest support Unimplemented");
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exit(1);
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}
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#if 0
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}
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#endif
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/* Index Process Table by PID to Find Corresponding Process Table Entry */
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offset = pid * sizeof(struct prtb_entry);
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size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
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if (offset >= size) {
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/* offset exceeds size of the process table */
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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return 1;
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}
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#ifdef UNICORN_ARCH_POSTFIX
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prtbe0 = glue(ldq_phys, UNICORN_ARCH_POSTFIX)(cs->uc, cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
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#else
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prtbe0 = ldq_phys(cs->uc, cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
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#endif
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/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
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page_size = PRTBE_R_GET_RTS(prtbe0);
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pte = ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK,
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prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
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&raddr, &page_size, &fault_cause, &pte_addr);
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if (!pte || ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, &prot)) {
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/* Couldn't get pte or access denied due to protection */
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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return 1;
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}
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/* Update Reference and Change Bits */
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ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, &prot);
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tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
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prot, mmu_idx, 1ULL << page_size);
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return 0;
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}
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hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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#if 0
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PPCVirtualHypervisorClass *vhc;
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#endif
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hwaddr raddr, pte_addr;
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uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
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int page_size, fault_cause = 0;
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ppc_v3_pate_t pate;
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/* Handle Real Mode */
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if (msr_dr == 0) {
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/* In real mode top 4 effective addr bits (mostly) ignored */
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return eaddr & 0x0FFFFFFFFFFFFFFFULL;
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}
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/* Virtual Mode Access - get the fully qualified address */
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if (!ppc_radix64_get_fully_qualified_addr(env, eaddr, &lpid, &pid)) {
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return -1;
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}
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/* Get Process Table */
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#if 0
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if (cpu->vhyp) {
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vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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vhc->get_pate(cpu->vhyp, &pate);
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} else {
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#endif
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if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
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return -1;
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}
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if (!validate_pate(cpu, lpid, &pate)) {
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return -1;
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}
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/* We don't support guest mode yet */
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if (lpid != 0) {
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fprintf(stderr, "PowerNV guest support Unimplemented");
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exit(1);
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}
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#if 0
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}
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#endif
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/* Index Process Table by PID to Find Corresponding Process Table Entry */
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offset = pid * sizeof(struct prtb_entry);
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size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
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if (offset >= size) {
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/* offset exceeds size of the process table */
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return -1;
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}
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#ifdef UNICORN_ARCH_POSTFIX
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prtbe0 = glue(ldq_phys, UNICORN_ARCH_POSTFIX)(cs->uc, cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
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#else
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prtbe0 = ldq_phys(cs->uc, cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
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#endif
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/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
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page_size = PRTBE_R_GET_RTS(prtbe0);
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pte = ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK,
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prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
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&raddr, &page_size, &fault_cause, &pte_addr);
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if (!pte) {
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return -1;
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}
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return raddr & TARGET_PAGE_MASK;
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}
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