import Unicorn2
This commit is contained in:
Nguyen Anh Quynh
@@ -23,325 +23,134 @@
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*
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* Used by target op helpers.
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*
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* MMU mode suffixes are defined in target cpu.h.
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* The syntax for the accessors is:
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*
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* load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
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* cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)
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* cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
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*
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* store: cpu_st{size}_{mmusuffix}(env, ptr, val)
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* cpu_st{size}_{mmusuffix}_ra(env, ptr, val, retaddr)
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* cpu_st{size}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
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*
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* sign is:
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* (empty): for 32 and 64 bit sizes
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
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* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
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* the index to use; the "data" and "code" suffixes take the index from
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* cpu_mmu_index().
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*/
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#ifndef CPU_LDST_H
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#define CPU_LDST_H
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#if defined(CONFIG_USER_ONLY)
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/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
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#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
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#include "cpu-defs.h"
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#include "cpu.h"
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#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
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#define h2g_valid(x) 1
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#else
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#define h2g_valid(x) ({ \
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unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
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(__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
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(!RESERVED_VA || (__guest < RESERVED_VA)); \
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})
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typedef target_ulong abi_ptr;
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#define TARGET_ABI_FMT_ptr TARGET_ABI_FMT_lx
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uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
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uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
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void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t retaddr);
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void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t retaddr);
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void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t retaddr);
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void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
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uint64_t val, uintptr_t retaddr);
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/* Needed for TCG_OVERSIZED_GUEST */
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#include "tcg/tcg.h"
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static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry)
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{
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return entry->addr_write;
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}
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/* Find the TLB index corresponding to the mmu_idx + address pair. */
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static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx,
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target_ulong addr)
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{
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#ifdef TARGET_ARM
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struct uc_struct *uc = env->uc;
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#endif
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uintptr_t size_mask = env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS;
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#define h2g_nocheck(x) ({ \
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unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
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(abi_ulong)__ret; \
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})
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return (addr >> TARGET_PAGE_BITS) & size_mask;
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}
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#define h2g(x) ({ \
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/* Check if given address fits target address space */ \
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assert(h2g_valid(x)); \
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h2g_nocheck(x); \
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})
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/* Find the TLB entry corresponding to the mmu_idx + address pair. */
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static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
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target_ulong addr)
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{
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return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)];
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}
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#define saddr(x) g2h(x)
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#define laddr(x) g2h(x)
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uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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#else /* !CONFIG_USER_ONLY */
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/* NOTE: we use double casts if pointers and target_ulong have
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different sizes */
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#define saddr(x) (uint8_t *)(intptr_t)(x)
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#define laddr(x) (uint8_t *)(intptr_t)(x)
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#endif
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int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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#define ldub_raw(p) ldub_p(laddr((p)))
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#define ldsb_raw(p) ldsb_p(laddr((p)))
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#define lduw_raw(p) lduw_p(laddr((p)))
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#define ldsw_raw(p) ldsw_p(laddr((p)))
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#define ldl_raw(p) ldl_p(laddr((p)))
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#define ldq_raw(p) ldq_p(laddr((p)))
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#define ldfl_raw(p) ldfl_p(laddr((p)))
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#define ldfq_raw(p) ldfq_p(laddr((p)))
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#define stb_raw(p, v) stb_p(saddr((p)), v)
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#define stw_raw(p, v) stw_p(saddr((p)), v)
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#define stl_raw(p, v) stl_p(saddr((p)), v)
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#define stq_raw(p, v) stq_p(saddr((p)), v)
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#define stfl_raw(p, v) stfl_p(saddr((p)), v)
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#define stfq_raw(p, v) stfq_p(saddr((p)), v)
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void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
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int mmu_idx, uintptr_t retaddr);
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#if defined(CONFIG_USER_ONLY)
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uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
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uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr);
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/* if user mode, no other memory access functions */
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#define ldub(p) ldub_raw(p)
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#define ldsb(p) ldsb_raw(p)
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#define lduw(p) lduw_raw(p)
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#define ldsw(p) ldsw_raw(p)
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#define ldl(p) ldl_raw(p)
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#define ldq(p) ldq_raw(p)
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#define ldfl(p) ldfl_raw(p)
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#define ldfq(p) ldfq_raw(p)
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#define stb(p, v) stb_raw(p, v)
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#define stw(p, v) stw_raw(p, v)
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#define stl(p, v) stl_raw(p, v)
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#define stq(p, v) stq_raw(p, v)
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#define stfl(p, v) stfl_raw(p, v)
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#define stfq(p, v) stfq_raw(p, v)
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static inline int cpu_ldsb_code(CPUArchState *env, abi_ptr addr)
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{
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return (int8_t)cpu_ldub_code(env, addr);
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}
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#define cpu_ldub_code(env1, p) ldub_raw(p)
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#define cpu_ldsb_code(env1, p) ldsb_raw(p)
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#define cpu_lduw_code(env1, p) lduw_raw(p)
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#define cpu_ldsw_code(env1, p) ldsw_raw(p)
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#define cpu_ldl_code(env1, p) ldl_raw(p)
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#define cpu_ldq_code(env1, p) ldq_raw(p)
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#define cpu_ldub_data(env, addr) ldub_raw(addr)
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#define cpu_lduw_data(env, addr) lduw_raw(addr)
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#define cpu_ldsw_data(env, addr) ldsw_raw(addr)
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#define cpu_ldl_data(env, addr) ldl_raw(addr)
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#define cpu_ldq_data(env, addr) ldq_raw(addr)
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#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
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#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
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#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
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#define cpu_stq_data(env, addr, data) stq_raw(addr, data)
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#define cpu_ldub_kernel(env, addr) ldub_raw(addr)
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#define cpu_lduw_kernel(env, addr) lduw_raw(addr)
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#define cpu_ldsw_kernel(env, addr) ldsw_raw(addr)
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#define cpu_ldl_kernel(env, addr) ldl_raw(addr)
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#define cpu_ldq_kernel(env, addr) ldq_raw(addr)
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#define cpu_stb_kernel(env, addr, data) stb_raw(addr, data)
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#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
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#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
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#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
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#define ldub_kernel(p) ldub_raw(p)
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#define ldsb_kernel(p) ldsb_raw(p)
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#define lduw_kernel(p) lduw_raw(p)
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#define ldsw_kernel(p) ldsw_raw(p)
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#define ldl_kernel(p) ldl_raw(p)
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#define ldq_kernel(p) ldq_raw(p)
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#define ldfl_kernel(p) ldfl_raw(p)
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#define ldfq_kernel(p) ldfq_raw(p)
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#define stb_kernel(p, v) stb_raw(p, v)
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#define stw_kernel(p, v) stw_raw(p, v)
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#define stl_kernel(p, v) stl_raw(p, v)
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#define stq_kernel(p, v) stq_raw(p, v)
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#define stfl_kernel(p, v) stfl_raw(p, v)
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#define stfq_kernel(p, vt) stfq_raw(p, v)
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#define cpu_ldub_data(env, addr) ldub_raw(addr)
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#define cpu_lduw_data(env, addr) lduw_raw(addr)
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#define cpu_ldl_data(env, addr) ldl_raw(addr)
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#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
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#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
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#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
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#else
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/* XXX: find something cleaner.
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* Furthermore, this is false for 64 bits targets
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*/
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#define ldul_user ldl_user
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#define ldul_kernel ldl_kernel
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#define ldul_hypv ldl_hypv
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#define ldul_executive ldl_executive
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#define ldul_supervisor ldl_supervisor
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/* The memory helpers for tcg-generated code need tcg_target_long etc. */
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#include "tcg.h"
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uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint16_t helper_ldw_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint32_t helper_ldl_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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void helper_stb_mmu(CPUArchState *env, target_ulong addr,
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uint8_t val, int mmu_idx);
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void helper_stw_mmu(CPUArchState *env, target_ulong addr,
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uint16_t val, int mmu_idx);
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void helper_stl_mmu(CPUArchState *env, target_ulong addr,
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uint32_t val, int mmu_idx);
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void helper_stq_mmu(CPUArchState *env, target_ulong addr,
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uint64_t val, int mmu_idx);
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uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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#define CPU_MMU_INDEX 0
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#define MEMSUFFIX MMU_MODE0_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#define CPU_MMU_INDEX 1
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#define MEMSUFFIX MMU_MODE1_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#if (NB_MMU_MODES >= 3)
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#define CPU_MMU_INDEX 2
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#define MEMSUFFIX MMU_MODE2_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 3) */
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#if (NB_MMU_MODES >= 4)
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#define CPU_MMU_INDEX 3
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#define MEMSUFFIX MMU_MODE3_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 4) */
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#if (NB_MMU_MODES >= 5)
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#define CPU_MMU_INDEX 4
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#define MEMSUFFIX MMU_MODE4_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 5) */
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#if (NB_MMU_MODES >= 6)
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#define CPU_MMU_INDEX 5
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#define MEMSUFFIX MMU_MODE5_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 6) */
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#if (NB_MMU_MODES > 6)
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||||
#error "NB_MMU_MODES > 6 is not supported for now"
|
||||
#endif /* (NB_MMU_MODES > 6) */
|
||||
|
||||
/* these access are slower, they must be as rare as possible */
|
||||
#define CPU_MMU_INDEX (cpu_mmu_index(env))
|
||||
#define MEMSUFFIX _data
|
||||
#define DATA_SIZE 1
|
||||
#include "exec/cpu_ldst_template.h"
|
||||
|
||||
#define DATA_SIZE 2
|
||||
#include "exec/cpu_ldst_template.h"
|
||||
|
||||
#define DATA_SIZE 4
|
||||
#include "exec/cpu_ldst_template.h"
|
||||
|
||||
#define DATA_SIZE 8
|
||||
#include "exec/cpu_ldst_template.h"
|
||||
#undef CPU_MMU_INDEX
|
||||
#undef MEMSUFFIX
|
||||
|
||||
#define ldub(p) ldub_data(p)
|
||||
#define ldsb(p) ldsb_data(p)
|
||||
#define lduw(p) lduw_data(p)
|
||||
#define ldsw(p) ldsw_data(p)
|
||||
#define ldl(p) ldl_data(p)
|
||||
#define ldq(p) ldq_data(p)
|
||||
|
||||
#define stb(p, v) stb_data(p, v)
|
||||
#define stw(p, v) stw_data(p, v)
|
||||
#define stl(p, v) stl_data(p, v)
|
||||
#define stq(p, v) stq_data(p, v)
|
||||
|
||||
#define CPU_MMU_INDEX (cpu_mmu_index(env))
|
||||
#define MEMSUFFIX _code
|
||||
#define SOFTMMU_CODE_ACCESS
|
||||
|
||||
#define DATA_SIZE 1
|
||||
#include "exec/cpu_ldst_template.h"
|
||||
|
||||
#define DATA_SIZE 2
|
||||
#include "exec/cpu_ldst_template.h"
|
||||
|
||||
#define DATA_SIZE 4
|
||||
#include "exec/cpu_ldst_template.h"
|
||||
|
||||
#define DATA_SIZE 8
|
||||
#include "exec/cpu_ldst_template.h"
|
||||
|
||||
#undef CPU_MMU_INDEX
|
||||
#undef MEMSUFFIX
|
||||
#undef SOFTMMU_CODE_ACCESS
|
||||
static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
|
||||
{
|
||||
return (int16_t)cpu_lduw_code(env, addr);
|
||||
}
|
||||
|
||||
/**
|
||||
* tlb_vaddr_to_host:
|
||||
@@ -351,50 +160,12 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
|
||||
* @mmu_idx: MMU index to use for lookup
|
||||
*
|
||||
* Look up the specified guest virtual index in the TCG softmmu TLB.
|
||||
* If the TLB contains a host virtual address suitable for direct RAM
|
||||
* access, then return it. Otherwise (TLB miss, TLB entry is for an
|
||||
* I/O access, etc) return NULL.
|
||||
*
|
||||
* This is the equivalent of the initial fast-path code used by
|
||||
* TCG backends for guest load and store accesses.
|
||||
* If we can translate a host virtual address suitable for direct RAM
|
||||
* access, without causing a guest exception, then return it.
|
||||
* Otherwise (TLB entry is for an I/O access, guest software
|
||||
* TLB fill required, etc) return NULL.
|
||||
*/
|
||||
static inline void *tlb_vaddr_to_host(CPUArchState *env, target_ulong addr,
|
||||
int access_type, int mmu_idx)
|
||||
{
|
||||
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
||||
CPUTLBEntry *tlbentry = &env->tlb_table[mmu_idx][index];
|
||||
target_ulong tlb_addr;
|
||||
uintptr_t haddr;
|
||||
|
||||
switch (access_type) {
|
||||
case 0:
|
||||
tlb_addr = tlbentry->addr_read;
|
||||
break;
|
||||
case 1:
|
||||
tlb_addr = tlbentry->addr_write;
|
||||
break;
|
||||
case 2:
|
||||
tlb_addr = tlbentry->addr_code;
|
||||
break;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
if ((addr & TARGET_PAGE_MASK)
|
||||
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
|
||||
/* TLB entry is for a different page */
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (tlb_addr & ~TARGET_PAGE_MASK) {
|
||||
/* IO access */
|
||||
return NULL;
|
||||
}
|
||||
|
||||
haddr = (uintptr_t)(addr + env->tlb_table[mmu_idx][index].addend);
|
||||
return (void *)haddr;
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
|
||||
void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
|
||||
MMUAccessType access_type, int mmu_idx);
|
||||
|
||||
#endif /* CPU_LDST_H */
|
||||
|
||||
Reference in New Issue
Block a user