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renames the register constants so unicorn and capstone can compile together

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This commit is contained in:
mothran
2015-08-23 21:36:33 -07:00
parent 3e5ebc58a0
commit a167f7c456
29 changed files with 4130 additions and 4128 deletions
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4
regress/crash_tb.py
View File

@@ -20,7 +20,7 @@ mu.mem_write(CODE_ADDR, binary1)
# emu for maximum 1 sec.
mu.emu_start(CODE_ADDR, len(binary1), UC_SECOND_SCALE)
print("RAX = %x" %mu.reg_read(X86_REG_RAX))
print("RAX = %x" %mu.reg_read(UC_X86_REG_RAX))
# write machine code to be emulated to memory
mu.mem_write(CODE_ADDR, binary2)
@@ -28,5 +28,5 @@ mu.mem_write(CODE_ADDR, binary2)
# emu for maximum 1 sec.
mu.emu_start(CODE_ADDR, len(binary2), UC_SECOND_SCALE)
print("RAX = %x" %mu.reg_read(X86_REG_RAX))
print("RAX = %x" %mu.reg_read(UC_X86_REG_RAX))

6
regress/hang.py
View File

@@ -17,13 +17,13 @@ def hook_code(uc, address, size, user_data):
# callback for tracing Linux interrupt
def hook_intr(uc, intno, user_data):
# only handle Linux syscall
rip = uc.reg_read(X86_REG_RIP)
rip = uc.reg_read(UC_X86_REG_RIP)
if intno != 0x80:
print("=== 0x%x: got interrupt %x, quit" %(rip, intno));
uc.emu_stop()
return
eax = uc.reg_read(X86_REG_EAX)
eax = uc.reg_read(UC_X86_REG_EAX)
print(">>> 0x%x: interrupt 0x%x, EAX = 0x%x" %(rip, intno, eax))
@@ -40,7 +40,7 @@ mu.hook_add(UC_HOOK_CODE, hook_code)
mu.hook_add(UC_HOOK_INTR, hook_intr)
# setup stack
mu.reg_write(X86_REG_RSP, 1024 * 1024)
mu.reg_write(UC_X86_REG_RSP, 1024 * 1024)
# fill in memory with 0xCC (software breakpoint int 3)
for i in xrange(1 * 1024):

8
regress/wrong_rip.py
View File

@@ -16,17 +16,17 @@ mu.mem_write(0, binary1 + binary2)
# emu for maximum 1 instruction.
mu.emu_start(0, 5, 0, 1)
print("RAX = %u" %mu.reg_read(X86_REG_RAX))
print("RAX = %u" %mu.reg_read(UC_X86_REG_RAX))
pos = mu.reg_read(X86_REG_RIP)
pos = mu.reg_read(UC_X86_REG_RIP)
print("RIP = %x" %pos)
mu.emu_start(5, 10, 0, 1)
pos = mu.reg_read(X86_REG_RIP)
pos = mu.reg_read(UC_X86_REG_RIP)
print("RIP = %x" %pos)
print("RAX = %u" %mu.reg_read(X86_REG_RAX))
print("RAX = %u" %mu.reg_read(UC_X86_REG_RAX))

8
regress/wrong_rip2.py
View File

@@ -16,17 +16,17 @@ mu.mem_write(0, binary1 + binary2)
# emu for maximum 1 instruction.
mu.emu_start(0, 10, 0, 1)
print("RAX = %u" %mu.reg_read(X86_REG_RAX))
print("RAX = %u" %mu.reg_read(UC_X86_REG_RAX))
pos = mu.reg_read(X86_REG_RIP)
pos = mu.reg_read(UC_X86_REG_RIP)
print("RIP = %x" %pos)
mu.emu_start(5, 10, 0, 1)
pos = mu.reg_read(X86_REG_RIP)
pos = mu.reg_read(UC_X86_REG_RIP)
print("RIP = %x" %pos)
print("RAX = %u" %mu.reg_read(X86_REG_RAX))
print("RAX = %u" %mu.reg_read(UC_X86_REG_RAX))

4
regress/wrong_rip3.py
View File

@@ -15,9 +15,9 @@ mu.mem_write(0, binary1)
# emu for maximum 1 instruction.
mu.emu_start(0, 10, 0, 1)
print("EAX = %u" %mu.reg_read(X86_REG_EAX))
print("EAX = %u" %mu.reg_read(UC_X86_REG_EAX))
pos = mu.reg_read(X86_REG_EIP)
pos = mu.reg_read(UC_X86_REG_EIP)
print("EIP = %x" %pos)

8
regress/wrong_rip4.py
View File

@@ -16,17 +16,17 @@ pos = 0
# emu for maximum 1 instruction.
mu.emu_start(pos, len(binary1), 0, 1)
print("EAX = %u" %mu.reg_read(X86_REG_EAX))
print("EAX = %u" %mu.reg_read(UC_X86_REG_EAX))
pos = mu.reg_read(X86_REG_EIP)
pos = mu.reg_read(UC_X86_REG_EIP)
print("EIP = %x" %pos)
# emu to the end
mu.emu_start(pos, len(binary1))
print("EAX = %u" %mu.reg_read(X86_REG_EAX))
print("EAX = %u" %mu.reg_read(UC_X86_REG_EAX))
pos = mu.reg_read(X86_REG_EIP)
pos = mu.reg_read(UC_X86_REG_EIP)
print("EIP = %x" %pos)