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renames the register constants so unicorn and capstone can compile together

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This commit is contained in:
mothran
2015-08-23 21:36:33 -07:00
parent 3e5ebc58a0
commit a167f7c456
29 changed files with 4130 additions and 4128 deletions
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20
qemu/target-arm/unicorn_aarch64.c
View File

@@ -43,18 +43,18 @@ int arm64_reg_read(uch handle, unsigned int regid, void *value)
mycpu = first_cpu;
if (regid >= ARM64_REG_X0 && regid <= ARM64_REG_X28)
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[regid - ARM64_REG_X0];
if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28)
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0];
else {
switch(regid) {
default: break;
case ARM64_REG_X29:
case UC_ARM64_REG_X29:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[29];
break;
case ARM64_REG_X30:
case UC_ARM64_REG_X30:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[30];
break;
case ARM64_REG_PC:
case UC_ARM64_REG_PC:
*(uint64_t *)value = ARM_CPU(uc, mycpu)->env.pc;
break;
}
@@ -75,18 +75,18 @@ int arm64_reg_write(uch handle, unsigned int regid, void *value)
mycpu = first_cpu;
if (regid >= ARM64_REG_X0 && regid <= ARM64_REG_X28)
ARM_CPU(uc, mycpu)->env.xregs[regid - ARM64_REG_X0] = *(int64_t *)value;
if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28)
ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(int64_t *)value;
else {
switch(regid) {
default: break;
case ARM64_REG_X29:
case UC_ARM64_REG_X29:
ARM_CPU(uc, mycpu)->env.xregs[29] = *(int64_t *)value;
break;
case ARM64_REG_X30:
case UC_ARM64_REG_X30:
ARM_CPU(uc, mycpu)->env.xregs[30] = *(int64_t *)value;
break;
case ARM64_REG_PC:
case UC_ARM64_REG_PC:
ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;
break;
}

32
qemu/target-arm/unicorn_arm.c
View File

@@ -48,20 +48,20 @@ int arm_reg_read(uch handle, unsigned int regid, void *value)
break;
case UC_MODE_ARM:
case UC_MODE_THUMB:
if (regid >= ARM_REG_R0 && regid <= ARM_REG_R12)
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[regid - ARM_REG_R0];
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0];
else {
switch(regid) {
//case ARM_REG_SP:
case ARM_REG_R13:
//case UC_ARM_REG_SP:
case UC_ARM_REG_R13:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[13];
break;
//case ARM_REG_LR:
case ARM_REG_R14:
//case UC_ARM_REG_LR:
case UC_ARM_REG_R14:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[14];
break;
//case ARM_REG_PC:
case ARM_REG_R15:
//case UC_ARM_REG_PC:
case UC_ARM_REG_R15:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[15];
break;
}
@@ -91,20 +91,20 @@ int arm_reg_write(uch handle, unsigned int regid, void *value)
case UC_MODE_ARM:
case UC_MODE_THUMB:
if (regid >= ARM_REG_R0 && regid <= ARM_REG_R12)
ARM_CPU(uc, mycpu)->env.regs[regid - ARM_REG_R0] = *(int32_t *)value;
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(int32_t *)value;
else {
switch(regid) {
//case ARM_REG_SP:
case ARM_REG_R13:
//case UC_ARM_REG_SP:
case UC_ARM_REG_R13:
ARM_CPU(uc, mycpu)->env.regs[13] = *(int32_t *)value;
break;
//case ARM_REG_LR:
case ARM_REG_R14:
//case UC_ARM_REG_LR:
case UC_ARM_REG_R14:
ARM_CPU(uc, mycpu)->env.regs[14] = *(int32_t *)value;
break;
//case ARM_REG_PC:
case ARM_REG_R15:
//case UC_ARM_REG_PC:
case UC_ARM_REG_R15:
ARM_CPU(uc, mycpu)->env.regs[15] = *(int32_t *)value;
break;
}

496
qemu/target-i386/unicorn.c
View File

@@ -147,19 +147,19 @@ int x86_reg_read(uch handle, unsigned int regid, void *value)
case UC_MODE_16:
switch(regid) {
default: break;
case X86_REG_ES:
case UC_X86_REG_ES:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].selector;
return 0;
case X86_REG_SS:
case UC_X86_REG_SS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].selector;
return 0;
case X86_REG_DS:
case UC_X86_REG_DS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].selector;
return 0;
case X86_REG_FS:
case UC_X86_REG_FS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].selector;
return 0;
case X86_REG_GS:
case UC_X86_REG_GS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].selector;
return 0;
}
@@ -168,109 +168,109 @@ int x86_reg_read(uch handle, unsigned int regid, void *value)
switch(regid) {
default:
break;
case X86_REG_CR0 ... X86_REG_CR4:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - X86_REG_CR0];
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
break;
case X86_REG_DR0 ... X86_REG_DR7:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - X86_REG_DR0];
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
break;
case X86_REG_EFLAGS:
case UC_X86_REG_EFLAGS:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.eflags;
break;
case X86_REG_EAX:
case UC_X86_REG_EAX:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EAX];
break;
case X86_REG_AX:
case UC_X86_REG_AX:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
break;
case X86_REG_AH:
case UC_X86_REG_AH:
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
break;
case X86_REG_AL:
case UC_X86_REG_AL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
break;
case X86_REG_EBX:
case UC_X86_REG_EBX:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBX];
break;
case X86_REG_BX:
case UC_X86_REG_BX:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
break;
case X86_REG_BH:
case UC_X86_REG_BH:
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
break;
case X86_REG_BL:
case UC_X86_REG_BL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
break;
case X86_REG_ECX:
case UC_X86_REG_ECX:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ECX];
break;
case X86_REG_CX:
case UC_X86_REG_CX:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
break;
case X86_REG_CH:
case UC_X86_REG_CH:
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
break;
case X86_REG_CL:
case UC_X86_REG_CL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
break;
case X86_REG_EDX:
case UC_X86_REG_EDX:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDX];
break;
case X86_REG_DX:
case UC_X86_REG_DX:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
break;
case X86_REG_DH:
case UC_X86_REG_DH:
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
break;
case X86_REG_DL:
case UC_X86_REG_DL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
break;
case X86_REG_ESP:
case UC_X86_REG_ESP:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESP];
break;
case X86_REG_SP:
case UC_X86_REG_SP:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
break;
case X86_REG_EBP:
case UC_X86_REG_EBP:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBP];
break;
case X86_REG_BP:
case UC_X86_REG_BP:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
break;
case X86_REG_ESI:
case UC_X86_REG_ESI:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESI];
break;
case X86_REG_SI:
case UC_X86_REG_SI:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
break;
case X86_REG_EDI:
case UC_X86_REG_EDI:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDI];
break;
case X86_REG_DI:
case UC_X86_REG_DI:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
break;
case X86_REG_EIP:
case UC_X86_REG_EIP:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.eip;
break;
case X86_REG_IP:
case UC_X86_REG_IP:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
break;
case X86_REG_CS:
case UC_X86_REG_CS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_CS].base;
break;
case X86_REG_DS:
case UC_X86_REG_DS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].base;
break;
case X86_REG_SS:
case UC_X86_REG_SS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].base;
break;
case X86_REG_ES:
case UC_X86_REG_ES:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].base;
break;
case X86_REG_FS:
case UC_X86_REG_FS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].base;
break;
case X86_REG_GS:
case UC_X86_REG_GS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
break;
}
@@ -281,244 +281,244 @@ int x86_reg_read(uch handle, unsigned int regid, void *value)
switch(regid) {
default:
break;
case X86_REG_CR0 ... X86_REG_CR4:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - X86_REG_CR0];
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
break;
case X86_REG_DR0 ... X86_REG_DR7:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - X86_REG_DR0];
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
break;
case X86_REG_EFLAGS:
case UC_X86_REG_EFLAGS:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.eflags;
break;
case X86_REG_RAX:
case UC_X86_REG_RAX:
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EAX];
break;
case X86_REG_EAX:
case UC_X86_REG_EAX:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
break;
case X86_REG_AX:
case UC_X86_REG_AX:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
break;
case X86_REG_AH:
case UC_X86_REG_AH:
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
break;
case X86_REG_AL:
case UC_X86_REG_AL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
break;
case X86_REG_RBX:
case UC_X86_REG_RBX:
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBX];
break;
case X86_REG_EBX:
case UC_X86_REG_EBX:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
break;
case X86_REG_BX:
case UC_X86_REG_BX:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
break;
case X86_REG_BH:
case UC_X86_REG_BH:
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
break;
case X86_REG_BL:
case UC_X86_REG_BL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
break;
case X86_REG_RCX:
case UC_X86_REG_RCX:
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ECX];
break;
case X86_REG_ECX:
case UC_X86_REG_ECX:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
break;
case X86_REG_CX:
case UC_X86_REG_CX:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
break;
case X86_REG_CH:
case UC_X86_REG_CH:
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
break;
case X86_REG_CL:
case UC_X86_REG_CL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
break;
case X86_REG_RDX:
case UC_X86_REG_RDX:
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDX];
break;
case X86_REG_EDX:
case UC_X86_REG_EDX:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
break;
case X86_REG_DX:
case UC_X86_REG_DX:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
break;
case X86_REG_DH:
case UC_X86_REG_DH:
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
break;
case X86_REG_DL:
case UC_X86_REG_DL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
break;
case X86_REG_RSP:
case UC_X86_REG_RSP:
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESP];
break;
case X86_REG_ESP:
case UC_X86_REG_ESP:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
break;
case X86_REG_SP:
case UC_X86_REG_SP:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
break;
case X86_REG_SPL:
case UC_X86_REG_SPL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
break;
case X86_REG_RBP:
case UC_X86_REG_RBP:
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBP];
break;
case X86_REG_EBP:
case UC_X86_REG_EBP:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
break;
case X86_REG_BP:
case UC_X86_REG_BP:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
break;
case X86_REG_BPL:
case UC_X86_REG_BPL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
break;
case X86_REG_RSI:
case UC_X86_REG_RSI:
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESI];
break;
case X86_REG_ESI:
case UC_X86_REG_ESI:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
break;
case X86_REG_SI:
case UC_X86_REG_SI:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
break;
case X86_REG_SIL:
case UC_X86_REG_SIL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
break;
case X86_REG_RDI:
case UC_X86_REG_RDI:
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDI];
break;
case X86_REG_EDI:
case UC_X86_REG_EDI:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
break;
case X86_REG_DI:
case UC_X86_REG_DI:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
break;
case X86_REG_DIL:
case UC_X86_REG_DIL:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
break;
case X86_REG_RIP:
case UC_X86_REG_RIP:
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.eip;
break;
case X86_REG_EIP:
case UC_X86_REG_EIP:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.eip);
break;
case X86_REG_IP:
case UC_X86_REG_IP:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
break;
case X86_REG_CS:
case UC_X86_REG_CS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_CS].base;
break;
case X86_REG_DS:
case UC_X86_REG_DS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].base;
break;
case X86_REG_SS:
case UC_X86_REG_SS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].base;
break;
case X86_REG_ES:
case UC_X86_REG_ES:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].base;
break;
case X86_REG_FS:
case UC_X86_REG_FS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].base;
break;
case X86_REG_GS:
case UC_X86_REG_GS:
*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
break;
case X86_REG_R8:
case UC_X86_REG_R8:
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[8]);
break;
case X86_REG_R8D:
case UC_X86_REG_R8D:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[8]);
break;
case X86_REG_R8W:
case UC_X86_REG_R8W:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[8]);
break;
case X86_REG_R8B:
case UC_X86_REG_R8B:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8]);
break;
case X86_REG_R9:
case UC_X86_REG_R9:
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[9]);
break;
case X86_REG_R9D:
case UC_X86_REG_R9D:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[9]);
break;
case X86_REG_R9W:
case UC_X86_REG_R9W:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[9]);
break;
case X86_REG_R9B:
case UC_X86_REG_R9B:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9]);
break;
case X86_REG_R10:
case UC_X86_REG_R10:
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[10]);
break;
case X86_REG_R10D:
case UC_X86_REG_R10D:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[10]);
break;
case X86_REG_R10W:
case UC_X86_REG_R10W:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[10]);
break;
case X86_REG_R10B:
case UC_X86_REG_R10B:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10]);
break;
case X86_REG_R11:
case UC_X86_REG_R11:
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[11]);
break;
case X86_REG_R11D:
case UC_X86_REG_R11D:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[11]);
break;
case X86_REG_R11W:
case UC_X86_REG_R11W:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[11]);
break;
case X86_REG_R11B:
case UC_X86_REG_R11B:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11]);
break;
case X86_REG_R12:
case UC_X86_REG_R12:
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[12]);
break;
case X86_REG_R12D:
case UC_X86_REG_R12D:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[12]);
break;
case X86_REG_R12W:
case UC_X86_REG_R12W:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[12]);
break;
case X86_REG_R12B:
case UC_X86_REG_R12B:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12]);
break;
case X86_REG_R13:
case UC_X86_REG_R13:
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[13]);
break;
case X86_REG_R13D:
case UC_X86_REG_R13D:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[13]);
break;
case X86_REG_R13W:
case UC_X86_REG_R13W:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[13]);
break;
case X86_REG_R13B:
case UC_X86_REG_R13B:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13]);
break;
case X86_REG_R14:
case UC_X86_REG_R14:
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[14]);
break;
case X86_REG_R14D:
case UC_X86_REG_R14D:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[14]);
break;
case X86_REG_R14W:
case UC_X86_REG_R14W:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[14]);
break;
case X86_REG_R14B:
case UC_X86_REG_R14B:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14]);
break;
case X86_REG_R15:
case UC_X86_REG_R15:
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[15]);
break;
case X86_REG_R15D:
case UC_X86_REG_R15D:
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[15]);
break;
case X86_REG_R15W:
case UC_X86_REG_R15W:
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[15]);
break;
case X86_REG_R15B:
case UC_X86_REG_R15B:
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15]);
break;
}
@@ -550,19 +550,19 @@ int x86_reg_write(uch handle, unsigned int regid, void *value)
case UC_MODE_16:
switch(regid) {
default: break;
case X86_REG_ES:
case UC_X86_REG_ES:
X86_CPU(uc, mycpu)->env.segs[R_ES].selector = *(int16_t *)value;
return 0;
case X86_REG_SS:
case UC_X86_REG_SS:
X86_CPU(uc, mycpu)->env.segs[R_SS].selector = *(int16_t *)value;
return 0;
case X86_REG_DS:
case UC_X86_REG_DS:
X86_CPU(uc, mycpu)->env.segs[R_DS].selector = *(int16_t *)value;
return 0;
case X86_REG_FS:
case UC_X86_REG_FS:
X86_CPU(uc, mycpu)->env.segs[R_FS].selector = *(int16_t *)value;
return 0;
case X86_REG_GS:
case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].selector = *(int16_t *)value;
return 0;
}
@@ -571,109 +571,109 @@ int x86_reg_write(uch handle, unsigned int regid, void *value)
switch(regid) {
default:
break;
case X86_REG_CR0 ... X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - X86_REG_CR0] = *(int32_t *)value;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(int32_t *)value;
break;
case X86_REG_DR0 ... X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - X86_REG_DR0] = *(int32_t *)value;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(int32_t *)value;
break;
case X86_REG_EFLAGS:
case UC_X86_REG_EFLAGS:
X86_CPU(uc, mycpu)->env.eflags = *(int32_t *)value;
break;
case X86_REG_EAX:
case UC_X86_REG_EAX:
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(int32_t *)value;
break;
case X86_REG_AX:
case UC_X86_REG_AX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int16_t *)value);
break;
case X86_REG_AH:
case UC_X86_REG_AH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value);
break;
case X86_REG_AL:
case UC_X86_REG_AL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value);
break;
case X86_REG_EBX:
case UC_X86_REG_EBX:
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(int32_t *)value;
break;
case X86_REG_BX:
case UC_X86_REG_BX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int16_t *)value);
break;
case X86_REG_BH:
case UC_X86_REG_BH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value);
break;
case X86_REG_BL:
case UC_X86_REG_BL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value);
break;
case X86_REG_ECX:
case UC_X86_REG_ECX:
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(int32_t *)value;
break;
case X86_REG_CX:
case UC_X86_REG_CX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int16_t *)value);
break;
case X86_REG_CH:
case UC_X86_REG_CH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value);
break;
case X86_REG_CL:
case UC_X86_REG_CL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value);
break;
case X86_REG_EDX:
case UC_X86_REG_EDX:
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(int32_t *)value;
break;
case X86_REG_DX:
case UC_X86_REG_DX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int16_t *)value);
break;
case X86_REG_DH:
case UC_X86_REG_DH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value);
break;
case X86_REG_DL:
case UC_X86_REG_DL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value);
break;
case X86_REG_ESP:
case UC_X86_REG_ESP:
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(int32_t *)value;
break;
case X86_REG_SP:
case UC_X86_REG_SP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int16_t *)value);
break;
case X86_REG_EBP:
case UC_X86_REG_EBP:
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(int32_t *)value;
break;
case X86_REG_BP:
case UC_X86_REG_BP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int16_t *)value);
break;
case X86_REG_ESI:
case UC_X86_REG_ESI:
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(int32_t *)value;
break;
case X86_REG_SI:
case UC_X86_REG_SI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int16_t *)value);
break;
case X86_REG_EDI:
case UC_X86_REG_EDI:
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(int32_t *)value;
break;
case X86_REG_DI:
case UC_X86_REG_DI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int16_t *)value);
break;
case X86_REG_EIP:
case UC_X86_REG_EIP:
X86_CPU(uc, mycpu)->env.eip = *(int32_t *)value;
break;
case X86_REG_IP:
case UC_X86_REG_IP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(int16_t *)value);
break;
case X86_REG_CS:
case UC_X86_REG_CS:
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(int16_t *)value;
break;
case X86_REG_DS:
case UC_X86_REG_DS:
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(int16_t *)value;
break;
case X86_REG_SS:
case UC_X86_REG_SS:
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(int16_t *)value;
break;
case X86_REG_ES:
case UC_X86_REG_ES:
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(int16_t *)value;
break;
case X86_REG_FS:
case UC_X86_REG_FS:
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(int16_t *)value;
break;
case X86_REG_GS:
case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(int16_t *)value;
break;
}
@@ -684,244 +684,244 @@ int x86_reg_write(uch handle, unsigned int regid, void *value)
switch(regid) {
default:
break;
case X86_REG_CR0 ... X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - X86_REG_CR0] = *(int64_t *)value;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(int64_t *)value;
break;
case X86_REG_DR0 ... X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - X86_REG_DR0] = *(int64_t *)value;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(int64_t *)value;
break;
case X86_REG_EFLAGS:
case UC_X86_REG_EFLAGS:
X86_CPU(uc, mycpu)->env.eflags = *(int64_t *)value;
break;
case X86_REG_RAX:
case UC_X86_REG_RAX:
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(int64_t *)value;
break;
case X86_REG_EAX:
case UC_X86_REG_EAX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int32_t *)value);
break;
case X86_REG_AX:
case UC_X86_REG_AX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int16_t *)value);
break;
case X86_REG_AH:
case UC_X86_REG_AH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value);
break;
case X86_REG_AL:
case UC_X86_REG_AL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value);
break;
case X86_REG_RBX:
case UC_X86_REG_RBX:
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(int64_t *)value;
break;
case X86_REG_EBX:
case UC_X86_REG_EBX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int32_t *)value);
break;
case X86_REG_BX:
case UC_X86_REG_BX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int16_t *)value);
break;
case X86_REG_BH:
case UC_X86_REG_BH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value);
break;
case X86_REG_BL:
case UC_X86_REG_BL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value);
break;
case X86_REG_RCX:
case UC_X86_REG_RCX:
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(int64_t *)value;
break;
case X86_REG_ECX:
case UC_X86_REG_ECX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int32_t *)value);
break;
case X86_REG_CX:
case UC_X86_REG_CX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int16_t *)value);
break;
case X86_REG_CH:
case UC_X86_REG_CH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value);
break;
case X86_REG_CL:
case UC_X86_REG_CL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value);
break;
case X86_REG_RDX:
case UC_X86_REG_RDX:
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(int64_t *)value;
break;
case X86_REG_EDX:
case UC_X86_REG_EDX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int32_t *)value);
break;
case X86_REG_DX:
case UC_X86_REG_DX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int16_t *)value);
break;
case X86_REG_DH:
case UC_X86_REG_DH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value);
break;
case X86_REG_DL:
case UC_X86_REG_DL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value);
break;
case X86_REG_RSP:
case UC_X86_REG_RSP:
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(int64_t *)value;
break;
case X86_REG_ESP:
case UC_X86_REG_ESP:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int32_t *)value);
break;
case X86_REG_SP:
case UC_X86_REG_SP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int16_t *)value);
break;
case X86_REG_SPL:
case UC_X86_REG_SPL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int8_t *)value);
break;
case X86_REG_RBP:
case UC_X86_REG_RBP:
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(int64_t *)value;
break;
case X86_REG_EBP:
case UC_X86_REG_EBP:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int32_t *)value);
break;
case X86_REG_BP:
case UC_X86_REG_BP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int16_t *)value);
break;
case X86_REG_BPL:
case UC_X86_REG_BPL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int8_t *)value);
break;
case X86_REG_RSI:
case UC_X86_REG_RSI:
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(int64_t *)value;
break;
case X86_REG_ESI:
case UC_X86_REG_ESI:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int32_t *)value);
break;
case X86_REG_SI:
case UC_X86_REG_SI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int16_t *)value);
break;
case X86_REG_SIL:
case UC_X86_REG_SIL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int8_t *)value);
break;
case X86_REG_RDI:
case UC_X86_REG_RDI:
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(int64_t *)value;
break;
case X86_REG_EDI:
case UC_X86_REG_EDI:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int32_t *)value);
break;
case X86_REG_DI:
case UC_X86_REG_DI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int16_t *)value);
break;
case X86_REG_DIL:
case UC_X86_REG_DIL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int8_t *)value);
break;
case X86_REG_RIP:
case UC_X86_REG_RIP:
X86_CPU(uc, mycpu)->env.eip = *(int64_t *)value;
break;
case X86_REG_EIP:
case UC_X86_REG_EIP:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.eip, *(int32_t *)value);
break;
case X86_REG_IP:
case UC_X86_REG_IP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(int16_t *)value);
break;
case X86_REG_CS:
case UC_X86_REG_CS:
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(int16_t *)value;
break;
case X86_REG_DS:
case UC_X86_REG_DS:
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(int16_t *)value;
break;
case X86_REG_SS:
case UC_X86_REG_SS:
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(int16_t *)value;
break;
case X86_REG_ES:
case UC_X86_REG_ES:
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(int16_t *)value;
break;
case X86_REG_FS:
case UC_X86_REG_FS:
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(int16_t *)value;
break;
case X86_REG_GS:
case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(int16_t *)value;
break;
case X86_REG_R8:
case UC_X86_REG_R8:
X86_CPU(uc, mycpu)->env.regs[8] = *(int64_t *)value;
break;
case X86_REG_R8D:
case UC_X86_REG_R8D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[8], *(int32_t *)value);
break;
case X86_REG_R8W:
case UC_X86_REG_R8W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[8], *(int16_t *)value);
break;
case X86_REG_R8B:
case UC_X86_REG_R8B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8], *(int8_t *)value);
break;
case X86_REG_R9:
case UC_X86_REG_R9:
X86_CPU(uc, mycpu)->env.regs[9] = *(int64_t *)value;
break;
case X86_REG_R9D:
case UC_X86_REG_R9D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[9], *(int32_t *)value);
break;
case X86_REG_R9W:
case UC_X86_REG_R9W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[9], *(int16_t *)value);
break;
case X86_REG_R9B:
case UC_X86_REG_R9B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9], *(int8_t *)value);
break;
case X86_REG_R10:
case UC_X86_REG_R10:
X86_CPU(uc, mycpu)->env.regs[10] = *(int64_t *)value;
break;
case X86_REG_R10D:
case UC_X86_REG_R10D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[10], *(int32_t *)value);
break;
case X86_REG_R10W:
case UC_X86_REG_R10W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[10], *(int16_t *)value);
break;
case X86_REG_R10B:
case UC_X86_REG_R10B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10], *(int8_t *)value);
break;
case X86_REG_R11:
case UC_X86_REG_R11:
X86_CPU(uc, mycpu)->env.regs[11] = *(int64_t *)value;
break;
case X86_REG_R11D:
case UC_X86_REG_R11D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[11], *(int32_t *)value);
break;
case X86_REG_R11W:
case UC_X86_REG_R11W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[11], *(int16_t *)value);
break;
case X86_REG_R11B:
case UC_X86_REG_R11B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11], *(int8_t *)value);
break;
case X86_REG_R12:
case UC_X86_REG_R12:
X86_CPU(uc, mycpu)->env.regs[12] = *(int64_t *)value;
break;
case X86_REG_R12D:
case UC_X86_REG_R12D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[12], *(int32_t *)value);
break;
case X86_REG_R12W:
case UC_X86_REG_R12W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[12], *(int16_t *)value);
break;
case X86_REG_R12B:
case UC_X86_REG_R12B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12], *(int8_t *)value);
break;
case X86_REG_R13:
case UC_X86_REG_R13:
X86_CPU(uc, mycpu)->env.regs[13] = *(int64_t *)value;
break;
case X86_REG_R13D:
case UC_X86_REG_R13D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[13], *(int32_t *)value);
break;
case X86_REG_R13W:
case UC_X86_REG_R13W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[13], *(int16_t *)value);
break;
case X86_REG_R13B:
case UC_X86_REG_R13B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13], *(int8_t *)value);
break;
case X86_REG_R14:
case UC_X86_REG_R14:
X86_CPU(uc, mycpu)->env.regs[14] = *(int64_t *)value;
break;
case X86_REG_R14D:
case UC_X86_REG_R14D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[14], *(int32_t *)value);
break;
case X86_REG_R14W:
case UC_X86_REG_R14W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[14], *(int16_t *)value);
break;
case X86_REG_R14B:
case UC_X86_REG_R14B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14], *(int8_t *)value);
break;
case X86_REG_R15:
case UC_X86_REG_R15:
X86_CPU(uc, mycpu)->env.regs[15] = *(int64_t *)value;
break;
case X86_REG_R15D:
case UC_X86_REG_R15D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[15], *(int32_t *)value);
break;
case X86_REG_R15W:
case UC_X86_REG_R15W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[15], *(int16_t *)value);
break;
case X86_REG_R15B:
case UC_X86_REG_R15B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(int8_t *)value);
break;
}

12
qemu/target-mips/unicorn.c
View File

@@ -37,12 +37,12 @@ int mips_reg_read(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu;
if (regid >= MIPS_REG_0 && regid <= MIPS_REG_31)
*(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - MIPS_REG_0];
if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
*(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0];
else {
switch(regid) {
default: break;
case MIPS_REG_PC:
case UC_MIPS_REG_PC:
*(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
break;
}
@@ -62,12 +62,12 @@ int mips_reg_write(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu;
if (regid >= MIPS_REG_0 && regid <= MIPS_REG_31)
MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - MIPS_REG_0] = *(int32_t *)value;
if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(int32_t *)value;
else {
switch(regid) {
default: break;
case MIPS_REG_PC:
case UC_MIPS_REG_PC:
MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(int32_t *)value;
break;
}

12
qemu/target-sparc/unicorn.c
View File

@@ -51,12 +51,12 @@ int sparc_reg_read(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu;
if (regid >= SPARC_REG_G0 && regid <= SPARC_REG_G7)
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - SPARC_REG_G0];
if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0];
else {
switch(regid) {
default: break;
case SPARC_REG_PC:
case UC_SPARC_REG_PC:
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc;
break;
}
@@ -76,12 +76,12 @@ int sparc_reg_write(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu;
if (regid >= SPARC_REG_G0 && regid <= SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - SPARC_REG_G0] = *(int32_t *)value;
if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(int32_t *)value;
else {
switch(regid) {
default: break;
case SPARC_REG_PC:
case UC_SPARC_REG_PC:
SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value;
SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4;
break;

12
qemu/target-sparc/unicorn64.c
View File

@@ -34,12 +34,12 @@ int sparc_reg_read(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu;
if (regid >= SPARC_REG_G0 && regid <= SPARC_REG_G7)
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - SPARC_REG_G0];
if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0];
else {
switch(regid) {
default: break;
case SPARC_REG_PC:
case UC_SPARC_REG_PC:
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc;
break;
}
@@ -59,12 +59,12 @@ int sparc_reg_write(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu;
if (regid >= SPARC_REG_G0 && regid <= SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - SPARC_REG_G0] = *(int32_t *)value;
if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(int32_t *)value;
else {
switch(regid) {
default: break;
case SPARC_REG_PC:
case UC_SPARC_REG_PC:
SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value;
SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4;
break;