Revamp Python regression tests suite (#2022)
* Fix Python regression test suite (partial) * Fix Python regression test suite * Add a test for mapping at high addresses * Add ctl tests
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@@ -3,33 +3,31 @@
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# This test demonstrates emulation behavior within and across
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# basic blocks.
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from __future__ import print_function
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import binascii
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import regress
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import struct
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import regress
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from unicorn import *
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from unicorn.x86_const import *
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CODE = binascii.unhexlify(b"".join([
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b"b800000000", # 1000: b8 00 00 00 00 mov eax,0x0
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b"40", # 1005: 40 inc eax
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b"40", # 1006: 40 inc eax
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b"6810100000", # 1007: 68 10 10 00 00 push 0x1010
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b"c3", # 100c: c3 ret
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b"cc", # 100d: cc int3
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b"cc", # 100e: cc int3
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b"cc", # 100f: cc int3
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b"b800000000", # 1010: b8 00 00 00 00 mov eax,0x0
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b"40", # 1015: 40 inc eax
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b"40", # 1016: 40 inc eax
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]))
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CODE = (
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b"\xb8\x00\x00\x00\x00" # 1000: mov eax,0x0
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b"\x40" # 1005: inc eax
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b"\x40" # 1006: inc eax
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b"\x68\x10\x10\x00\x00" # 1007: push 0x1010
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b"\xc3" # 100c: ret
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b"\xcc" # 100d: int3
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b"\xcc" # 100e: int3
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b"\xcc" # 100f: int3
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b"\xb8\x00\x00\x00\x00" # 1010: mov eax,0x0
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b"\x40" # 1015: inc eax
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b"\x40" # 1016: inc eax
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)
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def showpc(mu):
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pc = mu.reg_read(UC_X86_REG_EIP)
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print("pc: 0x%x" % (pc))
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regress.logger.debug("pc: 0x%x", mu.reg_read(UC_X86_REG_EIP))
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class RunAcrossBBTest(regress.RegressTest):
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@@ -38,13 +36,13 @@ class RunAcrossBBTest(regress.RegressTest):
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#######################################################################
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# emu SETUP
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#######################################################################
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print("\n---- test: run_all ----")
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regress.logger.debug("\n---- test: run_all ----")
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mu = Uc(UC_ARCH_X86, UC_MODE_32)
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def hook_code(uc, address, size, user_data):
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print(">>> Tracing instruction at 0x%x, instruction size = %u" %(address, size))
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regress.logger.debug(">>> Tracing instruction at 0x%x, instruction size = %u", address, size)
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mu.hook_add(UC_HOOK_CODE, hook_code)
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# base of CODE
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@@ -73,33 +71,34 @@ class RunAcrossBBTest(regress.RegressTest):
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# 1010: b8 00 00 00 00 mov eax,0x0 <-+
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# 1015: 40 inc eax <
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# 1016: 40 inc eax <
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self.assertEqual(0x1016, mu.reg_read(UC_X86_REG_EIP), "unexpected PC (2)")
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self.assertEqual(0x2800, mu.reg_read(UC_X86_REG_ESP), "unexpected SP (2)")
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showpc(mu)
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except UcError as e:
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eip = mu.reg_read(UC_X86_REG_EIP)
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if e.errno == UC_ERR_FETCH_UNMAPPED:
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# during initial test dev, bad fetch at 0x1010, but the data is there,
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# and this proves it
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print("!!! about to bail due to bad fetch... here's the data at PC:")
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print(binascii.hexlify(mu.mem_read(mu.reg_read(UC_X86_REG_EIP), 0x8)))
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self.assertFalse(True, "ERROR: %s @ 0x%x" % (e, mu.reg_read(UC_X86_REG_EIP)))
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# during initial test dev, bad fetch at 0x1010, but the data is there, and this proves it
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regress.logger.error("!!! about to bail due to bad fetch... here's the data at PC:")
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regress.logger.error(binascii.hexlify(mu.mem_read(eip, 8)))
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self.fail("ERROR: %s @ 0x%x" % (e, eip))
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def test_run_across_bb(self):
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try:
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#######################################################################
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# emu SETUP
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#######################################################################
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print("\n---- test: run_across_bb ----")
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regress.logger.debug("\n---- test: run_across_bb ----")
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mu = Uc(UC_ARCH_X86, UC_MODE_32)
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def hook_code(uc, address, size, user_data):
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print(">>> Tracing instruction at 0x%x, instruction size = %u" %(address, size))
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regress.logger.debug(">>> Tracing instruction at 0x%x, instruction size = %u", address, size)
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mu.hook_add(UC_HOOK_CODE, hook_code)
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# base of CODE
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@@ -111,8 +110,10 @@ class RunAcrossBBTest(regress.RegressTest):
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mu.reg_write(UC_X86_REG_EIP, 0x1000)
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mu.reg_write(UC_X86_REG_ESP, 0x2800)
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self.assertEqual(0x1000, mu.reg_read(UC_X86_REG_EIP), "unexpected PC")
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self.assertEqual(0x2800, mu.reg_read(UC_X86_REG_ESP), "unexpected SP")
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showpc(mu)
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@@ -182,13 +183,14 @@ class RunAcrossBBTest(regress.RegressTest):
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showpc(mu)
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except UcError as e:
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if e.errno == UC_ERR_FETCH_UNMAPPED:
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# during initial test dev, bad fetch at 0x1010, but the data is there,
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# and this proves it
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print("!!! about to bail due to bad fetch... here's the data at PC:")
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print(binascii.hexlify(mu.mem_read(mu.reg_read(UC_X86_REG_EIP), 0x8)))
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eip = mu.reg_read(UC_X86_REG_EIP)
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self.assertFalse(True, "ERROR: %s @ 0x%x" % (e, mu.reg_read(UC_X86_REG_EIP)))
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if e.errno == UC_ERR_FETCH_UNMAPPED:
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# during initial test dev, bad fetch at 0x1010, but the data is there, and this proves it
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regress.logger.error("!!! about to bail due to bad fetch... here's the data at PC:")
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regress.logger.error(binascii.hexlify(mu.mem_read(eip, 8)))
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self.fail("ERROR: %s @ 0x%x" % (e, eip))
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if __name__ == '__main__':
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