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- Improved the GitHub python binding workflow: (#2072)

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- Added fullMode input in workflow_dispatch
    - Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
    - Set proper artifact names
    - Removed not needed steps
    - Compacted some steps in order to leverage more the matrix feature
    - Bumped cibuildwheel action to 2.22.0
    - Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
This commit is contained in:
@Antelox
2024-12-29 15:24:48 +01:00
committed by GitHub
parent 07e8162cca
commit 9cfd5cfac3
85 changed files with 543 additions and 838 deletions
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41
tests/regress/x86_64_msr.py
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@@ -1,11 +1,7 @@
#!/usr/bin/env python
import regress
from unicorn import *
from unicorn.x86_const import *
CODE_ADDR = 0x40000
CODE_SIZE = 0x1000
@@ -15,16 +11,15 @@ SCRATCH_SIZE = 0x1000
SEGMENT_ADDR = 0x5000
SEGMENT_SIZE = 0x1000
FSMSR = 0xC0000100
GSMSR = 0xC0000101
def set_msr(uc, msr, value, scratch=SCRATCH_ADDR):
'''
"""
set the given model-specific register (MSR) to the given value.
this will clobber some memory at the given scratch address, as it emits some code.
'''
"""
# save clobbered registers
orax = uc.reg_read(UC_X86_REG_RAX)
ordx = uc.reg_read(UC_X86_REG_RDX)
@@ -37,7 +32,7 @@ def set_msr(uc, msr, value, scratch=SCRATCH_ADDR):
uc.reg_write(UC_X86_REG_RAX, value & 0xFFFFFFFF)
uc.reg_write(UC_X86_REG_RDX, (value >> 32) & 0xFFFFFFFF)
uc.reg_write(UC_X86_REG_RCX, msr & 0xFFFFFFFF)
uc.emu_start(scratch, scratch+len(buf), count=1)
uc.emu_start(scratch, scratch + len(buf), count=1)
# restore clobbered registers
uc.reg_write(UC_X86_REG_RAX, orax)
@@ -47,10 +42,10 @@ def set_msr(uc, msr, value, scratch=SCRATCH_ADDR):
def get_msr(uc, msr, scratch=SCRATCH_ADDR):
'''
"""
fetch the contents of the given model-specific register (MSR).
this will clobber some memory at the given scratch address, as it emits some code.
'''
"""
# save clobbered registers
orax = uc.reg_read(UC_X86_REG_RAX)
ordx = uc.reg_read(UC_X86_REG_RDX)
@@ -61,7 +56,7 @@ def get_msr(uc, msr, scratch=SCRATCH_ADDR):
buf = b'\x0f\x32'
uc.mem_write(scratch, buf)
uc.reg_write(UC_X86_REG_RCX, msr & 0xFFFFFFFF)
uc.emu_start(scratch, scratch+len(buf), count=1)
uc.emu_start(scratch, scratch + len(buf), count=1)
eax = uc.reg_read(UC_X86_REG_EAX)
edx = uc.reg_read(UC_X86_REG_EDX)
@@ -75,32 +70,32 @@ def get_msr(uc, msr, scratch=SCRATCH_ADDR):
def set_gs(uc, addr):
'''
"""
set the GS.base hidden descriptor-register field to the given address.
this enables referencing the gs segment on x86-64.
'''
"""
return set_msr(uc, GSMSR, addr)
def get_gs(uc):
'''
"""
fetch the GS.base hidden descriptor-register field.
'''
"""
return get_msr(uc, GSMSR)
def set_fs(uc, addr):
'''
"""
set the FS.base hidden descriptor-register field to the given address.
this enables referencing the fs segment on x86-64.
'''
"""
return set_msr(uc, FSMSR, addr)
def get_fs(uc):
'''
"""
fetch the FS.base hidden descriptor-register field.
'''
"""
return get_msr(uc, FSMSR)
@@ -124,12 +119,12 @@ class TestGetSetMSR(regress.RegressTest):
code = b'\x65\x48\x33\x0C\x25\x18\x00\x00\x00' # xor rcx, qword ptr gs:[0x18]
uc.mem_write(CODE_ADDR, code)
uc.mem_write(SEGMENT_ADDR+0x18, b'AAAAAAAA')
uc.mem_write(SEGMENT_ADDR + 0x18, b'AAAAAAAA')
set_gs(uc, SEGMENT_ADDR)
self.assertEqual(SEGMENT_ADDR, get_gs(uc))
uc.emu_start(CODE_ADDR, CODE_ADDR+len(code))
uc.emu_start(CODE_ADDR, CODE_ADDR + len(code))
self.assertEqual(uc.reg_read(UC_X86_REG_RCX), 0x4141414141414141)
@@ -142,12 +137,12 @@ class TestGetSetMSR(regress.RegressTest):
code = b'\x64\x48\x33\x0C\x25\x18\x00\x00\x00' # xor rcx, qword ptr fs:[0x18]
uc.mem_write(CODE_ADDR, code)
uc.mem_write(SEGMENT_ADDR+0x18, b'AAAAAAAA')
uc.mem_write(SEGMENT_ADDR + 0x18, b'AAAAAAAA')
set_fs(uc, SEGMENT_ADDR)
self.assertEqual(SEGMENT_ADDR, get_fs(uc))
uc.emu_start(CODE_ADDR, CODE_ADDR+len(code))
uc.emu_start(CODE_ADDR, CODE_ADDR + len(code))
self.assertEqual(uc.reg_read(UC_X86_REG_RCX), 0x4141414141414141)