- Improved the GitHub python binding workflow: (#2072)

- Added fullMode input in workflow_dispatch
    - Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
    - Set proper artifact names
    - Removed not needed steps
    - Compacted some steps in order to leverage more the matrix feature
    - Bumped cibuildwheel action to 2.22.0
    - Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf

tests/regress/wrong_rip.py

@@ -1,12 +1,10 @@
-#!/usr/bin/python
-
+import regress
 from unicorn import *
 from unicorn.x86_const import *
 
-import regress
+binary1 = b'\xb8\x02\x00\x00\x00'  # mov eax, 2
+binary2 = b'\xb8\x01\x00\x00\x00'  # mov eax, 1
 
-binary1 = b'\xb8\x02\x00\x00\x00'    # mov eax, 2
-binary2 = b'\xb8\x01\x00\x00\x00'    # mov eax, 1
 
 class WrongRIP(regress.RegressTest):
 
@@ -40,7 +38,7 @@ class WrongRIP(regress.RegressTest):
         self.assertEqual(0xa, mu.reg_read(UC_X86_REG_RIP))
 
     def test_step3(self):
-        bin3 = b'\x40\x01\xc1\x31\xf6' # inc eax; add ecx, eax; xor esi, esi
+        bin3 = b'\x40\x01\xc1\x31\xf6'  # inc eax; add ecx, eax; xor esi, esi
         mu = Uc(UC_ARCH_X86, UC_MODE_32)
         mu.mem_map(0, 2 * 1024 * 1024)
         # write machine code to be emulated to memory
@@ -51,7 +49,7 @@ class WrongRIP(regress.RegressTest):
         self.assertEqual(0x1, mu.reg_read(UC_X86_REG_EIP))
 
     def test_step_then_fin(self):
-        bin4 = b'\x40\x01\xc1\x31\xf6\x90\x90\x90' # inc eax; add ecx, eax; xor esi, esi
+        bin4 = b'\x40\x01\xc1\x31\xf6\x90\x90\x90'  # inc eax; add ecx, eax; xor esi, esi
         mu = Uc(UC_ARCH_X86, UC_MODE_32)
         mu.mem_map(0, 2 * 1024 * 1024)
         # write machine code to be emulated to memory
@@ -66,6 +64,6 @@ class WrongRIP(regress.RegressTest):
         self.assertEqual(0x1, mu.reg_read(UC_X86_REG_EAX))
         self.assertEqual(len(bin4), mu.reg_read(UC_X86_REG_EIP))
 
+
 if __name__ == '__main__':
     regress.main()
-