- Improved the GitHub python binding workflow: (#2072)

- Added fullMode input in workflow_dispatch
    - Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
    - Set proper artifact names
    - Removed not needed steps
    - Compacted some steps in order to leverage more the matrix feature
    - Bumped cibuildwheel action to 2.22.0
    - Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
This commit is contained in:
@Antelox
2024-12-29 15:24:48 +01:00
committed by GitHub
parent 07e8162cca
commit 9cfd5cfac3
85 changed files with 543 additions and 838 deletions

View File

@@ -1,11 +1,9 @@
#!/usr/bin/env python3
import regress
import sys
import unittest
from unicorn import Uc, UcError, UC_ARCH_X86, UC_MODE_64
from unicorn.unicorn_const import UC_TLB_VIRTUAL, UC_TLB_CPU, UC_ERR_FETCH_UNMAPPED
MAX_INTEL_INSN_SIZE = 15
@@ -23,8 +21,10 @@ class TestMem(regress.RegressTest):
self.uc.mem_map(address, 0x1000)
self.uc.mem_write(address, payload)
@unittest.skipIf(sys.version_info < (3, 7), reason="requires python3.7 or higher")
def test_virt_high_mapping(self):
"""Mapping memory at high addresses should work when TLB mode
"""
Mapping memory at high addresses should work when TLB mode
is set to VIRTUAL.
"""
@@ -42,8 +42,10 @@ class TestMem(regress.RegressTest):
except UcError:
self.fail('high mapping failed at %#018x' % code)
@unittest.skipIf(sys.version_info < (3, 7), reason="requires python3.7 or higher")
def test_cpu_high_mapping(self):
"""Mapping memory at high addresses should work fail TLB mode
"""
Mapping memory at high addresses should work fail TLB mode
is set to CPU (default).
"""