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- Improved the GitHub python binding workflow: (#2072)

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- Added fullMode input in workflow_dispatch
    - Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
    - Set proper artifact names
    - Removed not needed steps
    - Compacted some steps in order to leverage more the matrix feature
    - Bumped cibuildwheel action to 2.22.0
    - Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
This commit is contained in:
@Antelox
2024-12-29 15:24:48 +01:00
committed by GitHub
parent 07e8162cca
commit 9cfd5cfac3
85 changed files with 543 additions and 838 deletions
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58
tests/regress/arm_memcpy_neon.py
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@@ -1,44 +1,44 @@
import regress
import sys
import unittest
from unicorn import *
from unicorn.arm_const import *
SHELLCODE = bytes.fromhex(
'03 f0 8f e0' # 0001F894 ADD PC, PC, R3
'0d 07 21 f4' # 0001F898 VLD1.8 {D0}, [R1]!
'0d 07 0c f4' # 0001F89C VST1.8 {D0}, [R12]!
'0d 07 21 f4' # 0001F8A0 VLD1.8 {D0}, [R1]!
'0d 07 0c f4' # 0001F8A4 VST1.8 {D0}, [R12]!
'0d 07 21 f4' # 0001F8A8 VLD1.8 {D0}, [R1]!
'0d 07 0c f4' # 0001F8AC VST1.8 {D0}, [R12]!
'0d 07 21 f4' # 0001F8B0 VLD1.8 {D0}, [R1]!
'0d 07 0c f4' # 0001F8B4 VST1.8 {D0}, [R12]!
'0d 07 21 f4' # 0001F8B8 VLD1.8 {D0}, [R1]!
'0d 07 0c f4' # 0001F8BC VST1.8 {D0}, [R12]!
'0d 07 21 f4' # 0001F8C0 VLD1.8 {D0}, [R1]!
'0d 07 0c f4' # 0001F8C4 VST1.8 {D0}, [R12]!
'0d 07 21 f4' # 0001F8C8 VLD1.8 {D0}, [R1]!
'0d 07 0c f4' # 0001F8CC VST1.8 {D0}, [R12]!
'04 00 12 e3' # 0001F8D0 TST R2, #4
'04 30 91 14' # 0001F8D4 LDRNE R3, [R1],#4
'04 30 8c 14' # 0001F8D8 STRNE R3, [R12],#4
'82 2f b0 e1' # 0001F8DC MOVS R2, R2,LSL#31
'b2 30 d1 20' # 0001F8E0 LDRHCS R3, [R1],#2
'00 10 d1 15' # 0001F8E4 LDRBNE R1, [R1]
'b2 30 cc 20' # 0001F8E8 STRHCS R3, [R12],#2
'00 10 cc 15' # 0001F8EC STRBNE R1, [R12]
SHELLCODE = (
b'\x03\xF0\x8F\xE0' # 0001F894 ADD PC, PC, R3
b'\x0D\x07\x21\xF4' # 0001F898 VLD1.8 {D0}, [R1]!
b'\x0D\x07\x0C\xF4' # 0001F89C VST1.8 {D0}, [R12]!
b'\x0D\x07\x21\xF4' # 0001F8A0 VLD1.8 {D0}, [R1]!
b'\x0D\x07\x0C\xF4' # 0001F8A4 VST1.8 {D0}, [R12]!
b'\x0D\x07\x21\xF4' # 0001F8A8 VLD1.8 {D0}, [R1]!
b'\x0D\x07\x0C\xF4' # 0001F8AC VST1.8 {D0}, [R12]!
b'\x0D\x07\x21\xF4' # 0001F8B0 VLD1.8 {D0}, [R1]!
b'\x0D\x07\x0C\xF4' # 0001F8B4 VST1.8 {D0}, [R12]!
b'\x0D\x07\x21\xF4' # 0001F8B8 VLD1.8 {D0}, [R1]!
b'\x0D\x07\x0C\xF4' # 0001F8BC VST1.8 {D0}, [R12]!
b'\x0D\x07\x21\xF4' # 0001F8C0 VLD1.8 {D0}, [R1]!
b'\x0D\x07\x0C\xF4' # 0001F8C4 VST1.8 {D0}, [R12]!
b'\x0D\x07\x21\xF4' # 0001F8C8 VLD1.8 {D0}, [R1]!
b'\x0D\x07\x0C\xF4' # 0001F8CC VST1.8 {D0}, [R12]!
b'\x04\x00\x12\xE3' # 0001F8D0 TST R2, #4
b'\x04\x30\x91\x14' # 0001F8D4 LDRNE R3, [R1],#4
b'\x04\x30\x8C\x14' # 0001F8D8 STRNE R3, [R12],#4
b'\x82\x2F\xB0\xE1' # 0001F8DC MOVS R2, R2,LSL#31
b'\xB2\x30\xD1\x20' # 0001F8E0 LDRHCS R3, [R1],#2
b'\x00\x10\xD1\x15' # 0001F8E4 LDRBNE R1, [R1]
b'\xB2\x30\xCC\x20' # 0001F8E8 STRHCS R3, [R12],#2
b'\x00\x10\xCC\x15' # 0001F8EC STRBNE R1, [R12]
)
BASE = 0x1F894
COPY_SRC = 0x1000
COPY_DST = 0x2000
COPY_LEN = 8
DATA = b'c8' * COPY_LEN
class ArmMemcpy(regress.RegressTest):
@unittest.skipIf(sys.version_info < (3, 7), reason="requires python3.7 or higher")
def test_arm_memcpy(self):
uc = Uc(UC_ARCH_ARM, UC_MODE_ARM)
@@ -46,7 +46,7 @@ class ArmMemcpy(regress.RegressTest):
uc.mem_map(COPY_DST, 0x1000)
uc.mem_map(BASE & ~(0x1000 - 1), 0x1000)
uc.mem_write(COPY_SRC, DATA)
uc.mem_write(BASE, bytes(SHELLCODE))
uc.mem_write(BASE, SHELLCODE)
uc.reg_write_batch((
(UC_ARM_REG_R12, COPY_DST),