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Don't cache S390SkeyState and S390SkeysClass

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lazymio
2022-01-10 19:18:52 +01:00
parent 980eae7f44
commit 9ac796531a
4 changed files with 9 additions and 38 deletions
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11
qemu/target/s390x/mmu_helper.c
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@@ -283,9 +283,9 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
}
static void mmu_handle_skey(uc_engine *uc, target_ulong addr, int rw, int *flags)
{
static S390SKeysClass *skeyclass;
static S390SKeysState *ss;
{
S390SKeysState *ss = (S390SKeysState *)(&((S390CPU *)uc->cpu)->ss);
S390SKeysClass *skeyclass = S390_SKEYS_GET_CLASS(ss);
uint8_t key;
int rc;
@@ -295,11 +295,6 @@ static void mmu_handle_skey(uc_engine *uc, target_ulong addr, int rw, int *flags
}
#endif
if (unlikely(!ss)) {
ss = s390_get_skeys_device(uc);
skeyclass = S390_SKEYS_GET_CLASS(ss);
}
/*
* Whenever we create a new TLB entry, we set the storage key reference
* bit. In case we allow write accesses, we set the storage key change