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Add support for AArch Q regs

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This commit is contained in:
elicn
2022-09-13 16:33:43 +03:00
parent b8e656ae0d
commit 9290c7f277
1 changed files with 40 additions and 10 deletions
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50
bindings/python/unicorn/arch/arm.py
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@@ -10,6 +10,8 @@ from .. import Uc, UcError
from .. import arm_const as const from .. import arm_const as const
from ..unicorn_const import UC_ERR_ARG from ..unicorn_const import UC_ERR_ARG
from .types import UcReg128
ARMCPReg = Tuple[int, int, int, int, int, int, int] ARMCPReg = Tuple[int, int, int, int, int, int, int]
ARMCPRegValue = Tuple[int, int, int, int, int, int, int, int] ARMCPRegValue = Tuple[int, int, int, int, int, int, int, int]
@@ -43,17 +45,45 @@ class UcAArch32(Uc):
"""Unicorn subclass for ARM architecture. """Unicorn subclass for ARM architecture.
""" """
def reg_read(self, reg_id: int, aux: Any = None): REG_RANGE_Q = range(const.UC_ARM_REG_Q0, const.UC_ARM_REG_Q15 + 1)
if reg_id == const.UC_ARM_REG_CP_REG:
return self._reg_read(reg_id, UcRegCP, *aux)
# fallback to default reading method @staticmethod
return super().reg_read(reg_id, aux) def __select_reg_class(reg_id: int):
"""Select class for special architectural registers.
"""
reg_class = (
(UcAArch32.REG_RANGE_Q, UcReg128),
)
return next((cls for rng, cls in reg_class if reg_id in rng), None)
def reg_read(self, reg_id: int, aux: Any = None):
# select register class for special cases
reg_cls = UcAArch32.__select_reg_class(reg_id)
if reg_cls is None:
if reg_id == const.UC_ARM_REG_CP_REG:
return self._reg_read(reg_id, UcRegCP, *aux)
else:
# fallback to default reading method
return super().reg_read(reg_id, aux)
return self._reg_read(reg_id, reg_cls)
def reg_write(self, reg_id: int, value) -> None: def reg_write(self, reg_id: int, value) -> None:
if reg_id == const.UC_ARM_REG_CP_REG: # select register class for special cases
self._reg_write(reg_id, UcRegCP, value) reg_cls = UcAArch32.__select_reg_class(reg_id)
return
# fallback to default writing method if reg_cls is None:
super().reg_write(reg_id, value) if reg_id == const.UC_ARM_REG_CP_REG:
self._reg_write(reg_id, UcRegCP, value)
else:
# fallback to default writing method
super().reg_write(reg_id, value)
else:
self._reg_write(reg_id, reg_cls, value)