Arm support ported. (#736)
* Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
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xorstream
committed by
Nguyen Anh Quynh
Nguyen Anh Quynh
parent
fabe682d87
commit
8e45102b43
@@ -469,12 +469,16 @@ static void arm1026_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->reset_auxcr = 1;
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{
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/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
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ARMCPRegInfo ifar = {
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.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW,
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.fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
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.resetvalue = 0
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};
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ARMCPRegInfo ifar = { 0 };
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ifar.name = "IFAR";
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ifar.cp = 15;
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ifar.crn = 6;
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ifar.crm = 0;
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ifar.opc1 = 0;
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ifar.opc2 = 1;
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ifar.access = PL1_RW;
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ifar.fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]);
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ifar.resetvalue = 0;
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define_one_arm_cp_reg(cpu, &ifar);
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}
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}
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@@ -631,10 +635,10 @@ static void arm_v7m_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
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}
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static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
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{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ "L2LOCKDOWN", 15, 9, 0, 0,1,0, 0,
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ARM_CP_CONST, PL1_RW, NULL, 0, },
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{ "L2AUXCR", 15, 9, 0, 0,1,2, 0,
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ARM_CP_CONST, PL1_RW, NULL, 0, },
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REGINFO_SENTINEL
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};
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@@ -680,28 +684,28 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
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/* power_control should be set to maximum latency. Again,
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* default to 0 and set by private hook
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*/
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{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
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{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
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{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
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{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
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{ "A9_PWRCTL", 15,15,0, 0,0,0, 0,
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0, PL1_RW, NULL, 0,
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offsetof(CPUARMState, cp15.c15_power_control) },
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{ "A9_DIAG", 15,15,0, 0,0,1, 0,
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0, PL1_RW, NULL, 0,
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offsetof(CPUARMState, cp15.c15_diagnostic) },
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{ "A9_PWRDIAG",15,15,0, 0,0,2, 0,
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0, PL1_RW, NULL, 0,
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offsetof(CPUARMState, cp15.c15_power_diagnostic) },
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{ "NEONBUSY", 15,15,1, 0,0,0, 0,
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ARM_CP_CONST, PL1_RW, NULL, 0, },
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/* TLB lockdown control */
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{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
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.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
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{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
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.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
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{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
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{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
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{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
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{ "TLB_LOCKR", 15,15,4, 0,5,2, 0,
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ARM_CP_NOP, PL1_W, NULL, 0 },
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{ "TLB_LOCKW", 15,15,4, 0,5,4, 0,
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ARM_CP_NOP, PL1_W, NULL, 0, },
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{ "TLB_VA", 15,15,5, 0,5,2, 0,
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ARM_CP_CONST, PL1_RW, NULL, 0, },
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{ "TLB_PA", 15,15,6, 0,5,2, 0,
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ARM_CP_CONST, PL1_RW, NULL, 0 },
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{ "TLB_ATTR", 15,15,7, 0,5,2, 0,
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ARM_CP_CONST, PL1_RW, NULL, 0, },
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REGINFO_SENTINEL
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};
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@@ -759,12 +763,12 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
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#ifndef CONFIG_USER_ONLY
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{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
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.access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
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.writefn = arm_cp_write_ignore, },
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{ "L2CTLR", 15,9,0, 0,1,2, 0,
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0, PL1_RW, NULL, 0, 0, NULL, a15_l2ctlr_read,
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arm_cp_write_ignore, },
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#endif
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{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ "L2ECTLR", 15,9,0, 0,1,3, 0,
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ARM_CP_CONST, PL1_RW, NULL, 0 },
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REGINFO_SENTINEL
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};
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@@ -1005,43 +1009,42 @@ typedef struct ARMCPUInfo {
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static const ARMCPUInfo arm_cpus[] = {
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#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
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{ .name = "arm926", .initfn = arm926_initfn },
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{ .name = "arm946", .initfn = arm946_initfn },
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{ .name = "arm1026", .initfn = arm1026_initfn },
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{ "arm926", arm926_initfn },
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{ "arm946", arm946_initfn },
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{ "arm1026", arm1026_initfn },
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/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
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* older core than plain "arm1136". In particular this does not
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* have the v6K features.
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*/
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{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
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{ .name = "arm1136", .initfn = arm1136_initfn },
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{ .name = "arm1176", .initfn = arm1176_initfn },
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{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
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{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
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.class_init = arm_v7m_class_init },
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{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
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{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
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{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
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{ .name = "ti925t", .initfn = ti925t_initfn },
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{ .name = "sa1100", .initfn = sa1100_initfn },
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{ .name = "sa1110", .initfn = sa1110_initfn },
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{ .name = "pxa250", .initfn = pxa250_initfn },
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{ .name = "pxa255", .initfn = pxa255_initfn },
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{ .name = "pxa260", .initfn = pxa260_initfn },
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{ .name = "pxa261", .initfn = pxa261_initfn },
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{ .name = "pxa262", .initfn = pxa262_initfn },
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{ "arm1136-r2", arm1136_r2_initfn },
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{ "arm1136", arm1136_initfn },
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{ "arm1176", arm1176_initfn },
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{ "arm11mpcore", arm11mpcore_initfn },
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{ "cortex-m3", cortex_m3_initfn, arm_v7m_class_init },
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{ "cortex-a8", cortex_a8_initfn },
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{ "cortex-a9", cortex_a9_initfn },
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{ "cortex-a15", cortex_a15_initfn },
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{ "ti925t", ti925t_initfn },
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{ "sa1100", sa1100_initfn },
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{ "sa1110", sa1110_initfn },
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{ "pxa250", pxa250_initfn },
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{ "pxa255", pxa255_initfn },
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{ "pxa260", pxa260_initfn },
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{ "pxa261", pxa261_initfn },
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{ "pxa262", pxa262_initfn },
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/* "pxa270" is an alias for "pxa270-a0" */
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{ .name = "pxa270", .initfn = pxa270a0_initfn },
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{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
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{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
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{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
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{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
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{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
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{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
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{ "pxa270", pxa270a0_initfn },
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{ "pxa270-a0", pxa270a0_initfn },
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{ "pxa270-a1", pxa270a1_initfn },
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{ "pxa270-b0", pxa270b0_initfn },
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{ "pxa270-b1", pxa270b1_initfn },
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{ "pxa270-c0", pxa270c0_initfn },
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{ "pxa270-c5", pxa270c5_initfn },
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#ifdef CONFIG_USER_ONLY
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{ .name = "any", .initfn = arm_any_initfn },
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{ "any", arm_any_initfn },
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#endif
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#endif
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{ .name = NULL }
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{ NULL }
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};
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static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
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@@ -1073,13 +1076,12 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
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static void cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
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{
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TypeInfo type_info = {
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.parent = TYPE_ARM_CPU,
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.instance_size = sizeof(ARMCPU),
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.instance_init = info->initfn,
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.class_size = sizeof(ARMCPUClass),
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.class_init = info->class_init,
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};
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TypeInfo type_info = { 0 };
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type_info.parent = TYPE_ARM_CPU;
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type_info.instance_size = sizeof(ARMCPU);
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type_info.instance_init = info->initfn;
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type_info.class_size = sizeof(ARMCPUClass);
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type_info.class_init = info->class_init;
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type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
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type_register(uc, &type_info);
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@@ -1088,20 +1090,19 @@ static void cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
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void arm_cpu_register_types(void *opaque)
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{
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const TypeInfo arm_cpu_type_info = {
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.name = TYPE_ARM_CPU,
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.parent = TYPE_CPU,
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.instance_userdata = opaque,
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.instance_size = sizeof(ARMCPU),
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.instance_init = arm_cpu_initfn,
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.instance_post_init = arm_cpu_post_init,
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.instance_finalize = arm_cpu_finalizefn,
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.abstract = true,
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.class_size = sizeof(ARMCPUClass),
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.class_init = arm_cpu_class_init,
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};
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const ARMCPUInfo *info = arm_cpus;
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TypeInfo arm_cpu_type_info = { 0 };
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arm_cpu_type_info.name = TYPE_ARM_CPU,
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arm_cpu_type_info.parent = TYPE_CPU,
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arm_cpu_type_info.instance_userdata = opaque,
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arm_cpu_type_info.instance_size = sizeof(ARMCPU),
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arm_cpu_type_info.instance_init = arm_cpu_initfn,
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arm_cpu_type_info.instance_post_init = arm_cpu_post_init,
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arm_cpu_type_info.instance_finalize = arm_cpu_finalizefn,
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arm_cpu_type_info.abstract = true,
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arm_cpu_type_info.class_size = sizeof(ARMCPUClass),
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arm_cpu_type_info.class_init = arm_cpu_class_init,
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type_register_static(opaque, &arm_cpu_type_info);
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