riscv: Expose privilege level as pseudo-register PRIV (#1989)

Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.

The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.

The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.

bindings/python/unicorn/riscv_const.py

@@ -215,7 +215,8 @@ UC_RISCV_REG_F29 = 187
 UC_RISCV_REG_F30 = 188
 UC_RISCV_REG_F31 = 189
 UC_RISCV_REG_PC = 190
-UC_RISCV_REG_ENDING = 191
+UC_RISCV_REG_PRIV = 191
+UC_RISCV_REG_ENDING = 192
 
 # Alias registers
 UC_RISCV_REG_ZERO = 1