Automated leading tab to spaces conversion.
This commit is contained in:
xorstream
@@ -1,6 +1,6 @@
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/*
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refer to issue #575.
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to run correctly unicorn needs to be compiled for AArch64.
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refer to issue #575.
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to run correctly unicorn needs to be compiled for AArch64.
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*/
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#include "unicorn_test.h"
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@@ -9,94 +9,94 @@
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uint64_t trunc_page(uint64_t addr)
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{
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return (addr & ~(4095));
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return (addr & ~(4095));
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}
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/* Called before every test to set up a new instance */
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static int init(void **state)
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{
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printf("[+] Initializing Unicorn...\n");
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uc_engine *uc;
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printf("[+] Initializing Unicorn...\n");
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uc_engine *uc;
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if (uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc) != UC_ERR_OK) {
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printf("Error on open. Be sure that your unicorn library supports AArch64.\n");
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return -1;
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}
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if (uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc) != UC_ERR_OK) {
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printf("Error on open. Be sure that your unicorn library supports AArch64.\n");
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return -1;
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}
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*state = uc;
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*state = uc;
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return 0;
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return 0;
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}
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/* Called after every test to clean up */
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static int teardown(void **state)
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{
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printf("[+] Exiting...\n");
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uc_engine *uc = *state;
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printf("[+] Exiting...\n");
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uc_engine *uc = *state;
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uc_close(uc);
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uc_close(uc);
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*state = NULL;
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return 0;
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*state = NULL;
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return 0;
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}
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void test_hang(void **state)
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{
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uint32_t code[] = {
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0xd503201f, /* NOP */
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0xd503201f, /* NOP */
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0xd503201f, /* NOP */
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0xaa0103e0 /* MOV X0, X1 */
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};
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uint32_t code[] = {
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0xd503201f, /* NOP */
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0xd503201f, /* NOP */
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0xd503201f, /* NOP */
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0xaa0103e0 /* MOV X0, X1 */
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};
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uc_engine *uc = *state;
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uc_engine *uc = *state;
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uint64_t x0 = 0;
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uint64_t x1 = 1;
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uint64_t x0 = 0;
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uint64_t x1 = 1;
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/*
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* emulation will hang if some instruction hits every quarter of a page,
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* i.e. these offsets:
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* 0x1400, 0x1800, 0x1c00, 0x2000
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*
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* in this test, the code to be emulated is mapped just before the 0x1400
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* offset, so that the final instruction emulated (MOV X0, X1) hits the offset,
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* causing the hang.
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* If you try to write the code just four bytes behind, the hang doesn't occur.
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*
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* So far, this strange behaviour has only been observed with AArch64 Unicorn APIs.
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*/
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/*
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* emulation will hang if some instruction hits every quarter of a page,
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* i.e. these offsets:
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* 0x1400, 0x1800, 0x1c00, 0x2000
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*
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* in this test, the code to be emulated is mapped just before the 0x1400
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* offset, so that the final instruction emulated (MOV X0, X1) hits the offset,
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* causing the hang.
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* If you try to write the code just four bytes behind, the hang doesn't occur.
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*
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* So far, this strange behaviour has only been observed with AArch64 Unicorn APIs.
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*/
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uint64_t addr = 0x13f0; // try to map at (0x13f0 - 0x4) and the hang doesn't occur
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uint64_t trunc_addr = trunc_page(addr); // round down to nearest page
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uint64_t addr = 0x13f0; // try to map at (0x13f0 - 0x4) and the hang doesn't occur
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uint64_t trunc_addr = trunc_page(addr); // round down to nearest page
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uc_mem_map(uc, trunc_addr, 2 * 1024 * 1024, UC_PROT_ALL);
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uc_mem_map(uc, trunc_addr, 2 * 1024 * 1024, UC_PROT_ALL);
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if (uc_mem_write(uc, addr, &code, sizeof(code))) {
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printf("error on write\n");
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return;
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}
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if (uc_mem_write(uc, addr, &code, sizeof(code))) {
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printf("error on write\n");
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return;
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}
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uc_reg_write(uc, UC_ARM64_REG_X0, &x0);
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uc_reg_write(uc, UC_ARM64_REG_X1, &x1);
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uc_reg_write(uc, UC_ARM64_REG_X0, &x0);
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uc_reg_write(uc, UC_ARM64_REG_X1, &x1);
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if (uc_emu_start(uc, addr, addr + sizeof(code), 0, 0)) {
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printf("error on start\n");
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return;
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}
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if (uc_emu_start(uc, addr, addr + sizeof(code), 0, 0)) {
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printf("error on start\n");
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return;
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}
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uc_reg_read(uc, UC_ARM64_REG_X0, &x0);
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uc_reg_read(uc, UC_ARM64_REG_X1, &x1);
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uc_reg_read(uc, UC_ARM64_REG_X0, &x0);
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uc_reg_read(uc, UC_ARM64_REG_X1, &x1);
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printf("x0: %"PRIx64"\n", x0);
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printf("x1: %"PRIx64"\n", x1);
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printf("x0: %"PRIx64"\n", x0);
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printf("x1: %"PRIx64"\n", x1);
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}
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int main(int argc, const char * argv[]) {
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const struct CMUnitTest tests[] = {
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cmocka_unit_test_setup_teardown(test_hang, init, teardown),
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};
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const struct CMUnitTest tests[] = {
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cmocka_unit_test_setup_teardown(test_hang, init, teardown),
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};
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return cmocka_run_group_tests(tests, NULL, NULL);;
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return cmocka_run_group_tests(tests, NULL, NULL);;
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}
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@@ -16,24 +16,24 @@
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typedef struct _reg_value
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{
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uint32_t regId, regValue, mask;
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uint32_t regId, regValue, mask;
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} reg_value;
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typedef struct _instruction
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{
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const char* asmStr;
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uint8_t code[16]; //x86 inst == 15 bytes max
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uint32_t codeSize;
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reg_value* values;
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uint32_t nbValues;
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uint32_t addr;
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const char* asmStr;
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uint8_t code[16]; //x86 inst == 15 bytes max
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uint32_t codeSize;
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reg_value* values;
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uint32_t nbValues;
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uint32_t addr;
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} instruction;
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typedef struct _block
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{
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instruction* insts[255];
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uint32_t nbInsts;
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uint32_t size;
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instruction* insts[255];
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uint32_t nbInsts;
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uint32_t size;
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} block;
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/******************************************************************************/
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@@ -42,23 +42,23 @@ typedef struct _block
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#define CAT(X, Y) CAT2(X, Y)
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#define BLOCK_START(BLOCK) \
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{ \
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block* blockPtr = █ \
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blockPtr->nbInsts = 0; \
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instruction* instPtr = NULL;
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{ \
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block* blockPtr = █ \
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blockPtr->nbInsts = 0; \
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instruction* instPtr = NULL;
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#define BLOCK_END() }
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#define BLOCK_ADD(CODE_ASM, CODE) \
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const uint8_t CAT(code, __LINE__)[] = CODE; \
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instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, NULL, 0); \
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addInstructionToBlock(blockPtr, instPtr);
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const uint8_t CAT(code, __LINE__)[] = CODE; \
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instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, NULL, 0); \
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addInstructionToBlock(blockPtr, instPtr);
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#define BLOCK_ADD_CHECK(CODE_ASM, CODE, REGVALUES) \
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const uint8_t CAT(code, __LINE__)[] = CODE; \
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const reg_value CAT(regValues, __LINE__)[] = REGVALUES; \
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instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, CAT(regValues, __LINE__), sizeof(CAT(regValues, __LINE__)) / sizeof(reg_value)); \
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addInstructionToBlock(blockPtr, instPtr);
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const uint8_t CAT(code, __LINE__)[] = CODE; \
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const reg_value CAT(regValues, __LINE__)[] = REGVALUES; \
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instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, CAT(regValues, __LINE__), sizeof(CAT(regValues, __LINE__)) / sizeof(reg_value)); \
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addInstructionToBlock(blockPtr, instPtr);
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#define V(...) { __VA_ARGS__ }
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@@ -77,43 +77,43 @@ void initRegisters(uc_engine *uc);
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void hook_code_test_i386_shl(uc_engine *uc, uint64_t address, uint32_t size, void *user_data)
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{
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uint32_t i;
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block* b = (block*)user_data;
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instruction* currInst = getInstruction(b, (uint32_t)address);
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assert_true(currInst != NULL);
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uint32_t i;
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block* b = (block*)user_data;
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instruction* currInst = getInstruction(b, (uint32_t)address);
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assert_true(currInst != NULL);
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print_message("|\teip=%08x - %s\n", (uint32_t)address, currInst->asmStr);
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print_message("|\teip=%08x - %s\n", (uint32_t)address, currInst->asmStr);
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for (i = 0; i < currInst->nbValues; i++)
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{
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uint32_t regValue = getRegisterValue(uc, currInst->values[i].regId);
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print_message("|\t\ttesting %s : ", getRegisterName(currInst->values[i].regId));
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assert_int_equal(regValue & currInst->values[i].mask, currInst->values[i].regValue);
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print_message("ok\n");
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}
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for (i = 0; i < currInst->nbValues; i++)
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{
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uint32_t regValue = getRegisterValue(uc, currInst->values[i].regId);
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print_message("|\t\ttesting %s : ", getRegisterName(currInst->values[i].regId));
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assert_int_equal(regValue & currInst->values[i].mask, currInst->values[i].regValue);
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print_message("ok\n");
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}
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if (currInst->code[0] == 0xCC)
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OK(uc_emu_stop(uc));
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if (currInst->code[0] == 0xCC)
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OK(uc_emu_stop(uc));
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}
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bool hook_mem_invalid(uc_engine *uc, uc_mem_type type, uint64_t addr, int size, int64_t value, void *user_data)
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{
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switch (type)
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{
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default:
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print_message("hook_mem_invalid: UC_HOOK_MEM_INVALID type: %d at 0x%" PRIx64 "\n", type, addr); break;
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case UC_MEM_READ_UNMAPPED:
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print_message("hook_mem_invalid: Read from invalid memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break;
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case UC_MEM_WRITE_UNMAPPED:
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print_message("hook_mem_invalid: Write to invalid memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break;
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case UC_MEM_FETCH_PROT:
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print_message("hook_mem_invalid: Fetch from non-executable memory at 0x%" PRIx64 "\n", addr); break;
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case UC_MEM_WRITE_PROT:
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print_message("hook_mem_invalid: Write to non-writeable memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break;
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case UC_MEM_READ_PROT:
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print_message("hook_mem_invalid: Read from non-readable memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break;
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}
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return false;
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switch (type)
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{
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default:
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print_message("hook_mem_invalid: UC_HOOK_MEM_INVALID type: %d at 0x%" PRIx64 "\n", type, addr); break;
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case UC_MEM_READ_UNMAPPED:
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print_message("hook_mem_invalid: Read from invalid memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break;
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case UC_MEM_WRITE_UNMAPPED:
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print_message("hook_mem_invalid: Write to invalid memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break;
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case UC_MEM_FETCH_PROT:
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print_message("hook_mem_invalid: Fetch from non-executable memory at 0x%" PRIx64 "\n", addr); break;
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case UC_MEM_WRITE_PROT:
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print_message("hook_mem_invalid: Write to non-writeable memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break;
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case UC_MEM_READ_PROT:
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print_message("hook_mem_invalid: Read from non-readable memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break;
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}
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return false;
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}
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#define ADDR_CODE 0x100000
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@@ -123,311 +123,311 @@ bool hook_mem_invalid(uc_engine *uc, uc_mem_type type, uint64_t addr, int size,
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static void test_i386_shl_cl(void **state)
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{
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uc_engine *uc;
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uc_hook trace1;
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block b;
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uc_engine *uc;
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uc_hook trace1;
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block b;
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// Initialize emulator in X86-32bit mode
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OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
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OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
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initRegisters(uc);
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// Initialize emulator in X86-32bit mode
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OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
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OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
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initRegisters(uc);
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BLOCK_START(b);
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BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00));
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BLOCK_ADD_CHECK("mov cl, 2", V(0xB1, 0x02), V(V(UC_X86_REG_EBX, 0x3C, NO_MASK)));
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BLOCK_ADD_CHECK("shl ebx, cl", V(0xD3, 0xE3), V(V(UC_X86_REG_CL, 0x2, NO_MASK)));
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BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
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BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK)));
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BLOCK_END();
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BLOCK_START(b);
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BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00));
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BLOCK_ADD_CHECK("mov cl, 2", V(0xB1, 0x02), V(V(UC_X86_REG_EBX, 0x3C, NO_MASK)));
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BLOCK_ADD_CHECK("shl ebx, cl", V(0xD3, 0xE3), V(V(UC_X86_REG_CL, 0x2, NO_MASK)));
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BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
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BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK)));
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BLOCK_END();
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loadBlock(uc, &b, ADDR_CODE);
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loadBlock(uc, &b, ADDR_CODE);
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OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
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// emulate machine code in infinite time
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OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
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// emulate machine code in infinite time
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OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
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freeBlock(&b);
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freeBlock(&b);
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uc_close(uc);
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uc_close(uc);
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}
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static void test_i386_shl_imm(void **state)
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{
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uc_engine *uc;
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uc_hook trace1;
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block b;
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uc_engine *uc;
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uc_hook trace1;
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block b;
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// Initialize emulator in X86-32bit mode
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OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
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OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
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// Initialize emulator in X86-32bit mode
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OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
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OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
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initRegisters(uc);
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initRegisters(uc);
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BLOCK_START(b);
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BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00));
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BLOCK_ADD( "shl ebx, 2", V(0xC1, 0xE3, 0x02));
|
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BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
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BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK)));
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BLOCK_END();
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BLOCK_START(b);
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BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00));
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BLOCK_ADD( "shl ebx, 2", V(0xC1, 0xE3, 0x02));
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BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
|
||||
BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK)));
|
||||
BLOCK_END();
|
||||
|
||||
loadBlock(uc, &b, ADDR_CODE);
|
||||
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
|
||||
|
||||
// emulate machine code in infinite time
|
||||
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
|
||||
|
||||
freeBlock(&b);
|
||||
loadBlock(uc, &b, ADDR_CODE);
|
||||
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
|
||||
|
||||
// emulate machine code in infinite time
|
||||
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
|
||||
|
||||
freeBlock(&b);
|
||||
|
||||
uc_close(uc);
|
||||
uc_close(uc);
|
||||
}
|
||||
|
||||
static void test_i386_enter_leave(void **state)
|
||||
{
|
||||
uc_engine *uc;
|
||||
uc_hook trace1;
|
||||
block b;
|
||||
uc_engine *uc;
|
||||
uc_hook trace1;
|
||||
block b;
|
||||
|
||||
// Initialize emulator in X86-32bit mode
|
||||
OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
|
||||
OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
|
||||
OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL));
|
||||
// Initialize emulator in X86-32bit mode
|
||||
OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
|
||||
OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
|
||||
OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL));
|
||||
|
||||
initRegisters(uc);
|
||||
initRegisters(uc);
|
||||
|
||||
BLOCK_START(b);
|
||||
BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00));
|
||||
BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("enter 0x10,0", V(0xC8, 0x10, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_END();
|
||||
BLOCK_START(b);
|
||||
BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00));
|
||||
BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("enter 0x10,0", V(0xC8, 0x10, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_END();
|
||||
|
||||
loadBlock(uc, &b, ADDR_CODE);
|
||||
loadBlock(uc, &b, ADDR_CODE);
|
||||
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
|
||||
|
||||
// emulate machine code in infinite time
|
||||
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
|
||||
// emulate machine code in infinite time
|
||||
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
|
||||
|
||||
freeBlock(&b);
|
||||
freeBlock(&b);
|
||||
|
||||
uc_close(uc);
|
||||
uc_close(uc);
|
||||
}
|
||||
|
||||
static void test_i386_enter_nested_leave(void **state)
|
||||
{
|
||||
uc_engine *uc;
|
||||
uc_hook trace1;
|
||||
block b;
|
||||
uc_engine *uc;
|
||||
uc_hook trace1;
|
||||
block b;
|
||||
|
||||
// Initialize emulator in X86-32bit mode
|
||||
OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
|
||||
OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
|
||||
OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL));
|
||||
// Initialize emulator in X86-32bit mode
|
||||
OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
|
||||
OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
|
||||
OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL));
|
||||
|
||||
initRegisters(uc);
|
||||
initRegisters(uc);
|
||||
|
||||
BLOCK_START(b);
|
||||
BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00));
|
||||
BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov ebp, esp", V(0x89, 0xE5), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("enter 0x10,1", V(0xC8, 0x10, 0x00, 0x01), V(V(UC_X86_REG_EBP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 2*4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_END();
|
||||
BLOCK_START(b);
|
||||
BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00));
|
||||
BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov ebp, esp", V(0x89, 0xE5), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("enter 0x10,1", V(0xC8, 0x10, 0x00, 0x01), V(V(UC_X86_REG_EBP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 2*4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
|
||||
BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
|
||||
BLOCK_END();
|
||||
|
||||
loadBlock(uc, &b, ADDR_CODE);
|
||||
loadBlock(uc, &b, ADDR_CODE);
|
||||
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
|
||||
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
|
||||
|
||||
// emulate machine code in infinite time
|
||||
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
|
||||
// emulate machine code in infinite time
|
||||
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
|
||||
|
||||
freeBlock(&b);
|
||||
|
||||
uc_close(uc);
|
||||
freeBlock(&b);
|
||||
|
||||
uc_close(uc);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
int main(void) {
|
||||
const struct CMUnitTest tests[] = {
|
||||
const struct CMUnitTest tests[] = {
|
||||
|
||||
cmocka_unit_test(test_i386_shl_cl),
|
||||
cmocka_unit_test(test_i386_shl_imm),
|
||||
cmocka_unit_test(test_i386_enter_leave),
|
||||
cmocka_unit_test(test_i386_enter_nested_leave),
|
||||
};
|
||||
return cmocka_run_group_tests(tests, NULL, NULL);
|
||||
cmocka_unit_test(test_i386_shl_cl),
|
||||
cmocka_unit_test(test_i386_shl_imm),
|
||||
cmocka_unit_test(test_i386_enter_leave),
|
||||
cmocka_unit_test(test_i386_enter_nested_leave),
|
||||
};
|
||||
return cmocka_run_group_tests(tests, NULL, NULL);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
instruction* newInstruction(const uint8_t * _code, uint32_t _codeSize, const char* _asmStr, const reg_value* _values, uint32_t _nbValues)
|
||||
{
|
||||
instruction* inst = (instruction*)malloc(sizeof(instruction));
|
||||
instruction* inst = (instruction*)malloc(sizeof(instruction));
|
||||
|
||||
inst->asmStr = _asmStr;
|
||||
memcpy(inst->code, _code, _codeSize);
|
||||
inst->codeSize = _codeSize;
|
||||
inst->nbValues = 0;
|
||||
if (_values)
|
||||
{
|
||||
inst->values = (reg_value*)malloc(_nbValues*sizeof(reg_value));
|
||||
memcpy(inst->values, _values, _nbValues*sizeof(reg_value));
|
||||
inst->nbValues = _nbValues;
|
||||
}
|
||||
inst->asmStr = _asmStr;
|
||||
memcpy(inst->code, _code, _codeSize);
|
||||
inst->codeSize = _codeSize;
|
||||
inst->nbValues = 0;
|
||||
if (_values)
|
||||
{
|
||||
inst->values = (reg_value*)malloc(_nbValues*sizeof(reg_value));
|
||||
memcpy(inst->values, _values, _nbValues*sizeof(reg_value));
|
||||
inst->nbValues = _nbValues;
|
||||
}
|
||||
|
||||
return inst;
|
||||
return inst;
|
||||
}
|
||||
|
||||
void addInstructionToBlock(block* _b, instruction* _i)
|
||||
{
|
||||
_b->insts[_b->nbInsts++] = _i;
|
||||
_b->insts[_b->nbInsts++] = _i;
|
||||
}
|
||||
|
||||
uint32_t loadBlock(uc_engine *_uc, block* _block, uint32_t _at)
|
||||
{
|
||||
uint32_t i, j, offset;
|
||||
uint32_t i, j, offset;
|
||||
|
||||
for (i = 0, offset = 0; i < _block->nbInsts; i++)
|
||||
{
|
||||
const uint32_t codeSize = _block->insts[i]->codeSize;
|
||||
const uint8_t* code = _block->insts[i]->code;
|
||||
_block->insts[i]->addr = _at + offset;
|
||||
print_message("load: %08X: ", _block->insts[i]->addr);
|
||||
for (j = 0; j < codeSize; j++) print_message("%02X ", code[j]);
|
||||
for (j = 0; j < 15 - codeSize; j++) print_message(" ");
|
||||
print_message("%s\n", _block->insts[i]->asmStr);
|
||||
OK(uc_mem_write(_uc, _at + offset, code, codeSize));
|
||||
offset += codeSize;
|
||||
}
|
||||
_block->size = offset;
|
||||
return offset;
|
||||
for (i = 0, offset = 0; i < _block->nbInsts; i++)
|
||||
{
|
||||
const uint32_t codeSize = _block->insts[i]->codeSize;
|
||||
const uint8_t* code = _block->insts[i]->code;
|
||||
_block->insts[i]->addr = _at + offset;
|
||||
print_message("load: %08X: ", _block->insts[i]->addr);
|
||||
for (j = 0; j < codeSize; j++) print_message("%02X ", code[j]);
|
||||
for (j = 0; j < 15 - codeSize; j++) print_message(" ");
|
||||
print_message("%s\n", _block->insts[i]->asmStr);
|
||||
OK(uc_mem_write(_uc, _at + offset, code, codeSize));
|
||||
offset += codeSize;
|
||||
}
|
||||
_block->size = offset;
|
||||
return offset;
|
||||
}
|
||||
|
||||
void freeBlock(block* _block)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < _block->nbInsts; i++)
|
||||
{
|
||||
if (_block->insts[i]->nbValues > 0)
|
||||
free(_block->insts[i]->values);
|
||||
free(_block->insts[i]);
|
||||
}
|
||||
uint32_t i;
|
||||
for (i = 0; i < _block->nbInsts; i++)
|
||||
{
|
||||
if (_block->insts[i]->nbValues > 0)
|
||||
free(_block->insts[i]->values);
|
||||
free(_block->insts[i]);
|
||||
}
|
||||
}
|
||||
|
||||
void initRegisters(uc_engine *uc)
|
||||
{
|
||||
// initialize machine registers
|
||||
uint32_t zero = 0;
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EBP, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_ESP, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EDI, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_ESI, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EFLAGS, &zero));
|
||||
// initialize machine registers
|
||||
uint32_t zero = 0;
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EBP, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_ESP, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EDI, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_ESI, &zero));
|
||||
OK(uc_reg_write(uc, UC_X86_REG_EFLAGS, &zero));
|
||||
}
|
||||
|
||||
instruction* getInstruction(block* _block, uint32_t _addr)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < _block->nbInsts; i++)
|
||||
{
|
||||
if (_block->insts[i]->addr == _addr)
|
||||
return _block->insts[i];
|
||||
}
|
||||
return NULL;
|
||||
uint32_t i;
|
||||
for (i = 0; i < _block->nbInsts; i++)
|
||||
{
|
||||
if (_block->insts[i]->addr == _addr)
|
||||
return _block->insts[i];
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const char* getRegisterName(uint32_t _regid)
|
||||
{
|
||||
switch (_regid)
|
||||
{
|
||||
//8
|
||||
case UC_X86_REG_AH: return "AH";
|
||||
case UC_X86_REG_AL: return "AL";
|
||||
case UC_X86_REG_BH: return "BH";
|
||||
case UC_X86_REG_BL: return "BL";
|
||||
case UC_X86_REG_CL: return "CL";
|
||||
case UC_X86_REG_CH: return "CH";
|
||||
case UC_X86_REG_DH: return "DH";
|
||||
case UC_X86_REG_DL: return "DL";
|
||||
//16
|
||||
case UC_X86_REG_AX: return "AX";
|
||||
case UC_X86_REG_BX: return "BX";
|
||||
case UC_X86_REG_CX: return "CX";
|
||||
case UC_X86_REG_DX: return "DX";
|
||||
//32
|
||||
case UC_X86_REG_EAX: return "EAX";
|
||||
case UC_X86_REG_EBX: return "EBX";
|
||||
case UC_X86_REG_ECX: return "ECX";
|
||||
case UC_X86_REG_EDX: return "EDX";
|
||||
case UC_X86_REG_EDI: return "EDI";
|
||||
case UC_X86_REG_ESI: return "ESI";
|
||||
case UC_X86_REG_EBP: return "EBP";
|
||||
case UC_X86_REG_ESP: return "ESP";
|
||||
case UC_X86_REG_EIP: return "EIP";
|
||||
case UC_X86_REG_EFLAGS: return "EFLAGS";
|
||||
switch (_regid)
|
||||
{
|
||||
//8
|
||||
case UC_X86_REG_AH: return "AH";
|
||||
case UC_X86_REG_AL: return "AL";
|
||||
case UC_X86_REG_BH: return "BH";
|
||||
case UC_X86_REG_BL: return "BL";
|
||||
case UC_X86_REG_CL: return "CL";
|
||||
case UC_X86_REG_CH: return "CH";
|
||||
case UC_X86_REG_DH: return "DH";
|
||||
case UC_X86_REG_DL: return "DL";
|
||||
//16
|
||||
case UC_X86_REG_AX: return "AX";
|
||||
case UC_X86_REG_BX: return "BX";
|
||||
case UC_X86_REG_CX: return "CX";
|
||||
case UC_X86_REG_DX: return "DX";
|
||||
//32
|
||||
case UC_X86_REG_EAX: return "EAX";
|
||||
case UC_X86_REG_EBX: return "EBX";
|
||||
case UC_X86_REG_ECX: return "ECX";
|
||||
case UC_X86_REG_EDX: return "EDX";
|
||||
case UC_X86_REG_EDI: return "EDI";
|
||||
case UC_X86_REG_ESI: return "ESI";
|
||||
case UC_X86_REG_EBP: return "EBP";
|
||||
case UC_X86_REG_ESP: return "ESP";
|
||||
case UC_X86_REG_EIP: return "EIP";
|
||||
case UC_X86_REG_EFLAGS: return "EFLAGS";
|
||||
|
||||
default: fail();
|
||||
}
|
||||
return "UNKNOWN";
|
||||
default: fail();
|
||||
}
|
||||
return "UNKNOWN";
|
||||
}
|
||||
|
||||
uint32_t getRegisterValue(uc_engine *uc, uint32_t _regid)
|
||||
{
|
||||
switch (_regid)
|
||||
{
|
||||
//8
|
||||
case UC_X86_REG_AH: case UC_X86_REG_AL:
|
||||
case UC_X86_REG_BH: case UC_X86_REG_BL:
|
||||
case UC_X86_REG_CL: case UC_X86_REG_CH:
|
||||
case UC_X86_REG_DH: case UC_X86_REG_DL:
|
||||
{
|
||||
uint8_t val = 0;
|
||||
OK(uc_reg_read(uc, _regid, &val));
|
||||
return val;
|
||||
}
|
||||
//16
|
||||
case UC_X86_REG_AX: case UC_X86_REG_BX:
|
||||
case UC_X86_REG_CX: case UC_X86_REG_DX:
|
||||
{
|
||||
uint16_t val = 0;
|
||||
OK(uc_reg_read(uc, _regid, &val));
|
||||
return val;
|
||||
}
|
||||
//32
|
||||
case UC_X86_REG_EAX: case UC_X86_REG_EBX:
|
||||
case UC_X86_REG_ECX: case UC_X86_REG_EDX:
|
||||
case UC_X86_REG_EDI: case UC_X86_REG_ESI:
|
||||
case UC_X86_REG_EBP: case UC_X86_REG_ESP:
|
||||
case UC_X86_REG_EIP: case UC_X86_REG_EFLAGS:
|
||||
{
|
||||
uint32_t val = 0;
|
||||
OK(uc_reg_read(uc, _regid, &val));
|
||||
return val;
|
||||
}
|
||||
switch (_regid)
|
||||
{
|
||||
//8
|
||||
case UC_X86_REG_AH: case UC_X86_REG_AL:
|
||||
case UC_X86_REG_BH: case UC_X86_REG_BL:
|
||||
case UC_X86_REG_CL: case UC_X86_REG_CH:
|
||||
case UC_X86_REG_DH: case UC_X86_REG_DL:
|
||||
{
|
||||
uint8_t val = 0;
|
||||
OK(uc_reg_read(uc, _regid, &val));
|
||||
return val;
|
||||
}
|
||||
//16
|
||||
case UC_X86_REG_AX: case UC_X86_REG_BX:
|
||||
case UC_X86_REG_CX: case UC_X86_REG_DX:
|
||||
{
|
||||
uint16_t val = 0;
|
||||
OK(uc_reg_read(uc, _regid, &val));
|
||||
return val;
|
||||
}
|
||||
//32
|
||||
case UC_X86_REG_EAX: case UC_X86_REG_EBX:
|
||||
case UC_X86_REG_ECX: case UC_X86_REG_EDX:
|
||||
case UC_X86_REG_EDI: case UC_X86_REG_ESI:
|
||||
case UC_X86_REG_EBP: case UC_X86_REG_ESP:
|
||||
case UC_X86_REG_EIP: case UC_X86_REG_EFLAGS:
|
||||
{
|
||||
uint32_t val = 0;
|
||||
OK(uc_reg_read(uc, _regid, &val));
|
||||
return val;
|
||||
}
|
||||
|
||||
default: fail();
|
||||
}
|
||||
return 0;
|
||||
default: fail();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user