From 6c319941a5462ee3a4af4593c371f5674394d6ce Mon Sep 17 00:00:00 2001 From: cfrantz Date: Wed, 27 Feb 2019 17:55:27 -0800 Subject: [PATCH] Add support for the ARM IPSR register. (#1067) 1. Create an enum name for the IPSR register. 2. Implement read and write of the IPSR via the xpsr helper functions. Fixes #1065 --- include/unicorn/arm.h | 1 + qemu/target-arm/unicorn_arm.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/include/unicorn/arm.h b/include/unicorn/arm.h index f9130057..2726d147 100644 --- a/include/unicorn/arm.h +++ b/include/unicorn/arm.h @@ -133,6 +133,7 @@ typedef enum uc_arm_reg { UC_ARM_REG_C13_C0_2, UC_ARM_REG_C13_C0_3, + UC_ARM_REG_IPSR, UC_ARM_REG_ENDING, // <-- mark the end of the list or registers //> alias registers diff --git a/qemu/target-arm/unicorn_arm.c b/qemu/target-arm/unicorn_arm.c index d64d4a0d..cae0fdf2 100644 --- a/qemu/target-arm/unicorn_arm.c +++ b/qemu/target-arm/unicorn_arm.c @@ -90,6 +90,9 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun case UC_ARM_REG_FPEXC: *(int32_t *)value = ARM_CPU(uc, mycpu)->env.vfp.xregs[ARM_VFP_FPEXC]; break; + case UC_ARM_REG_IPSR: + *(uint32_t *)value = xpsr_read(&ARM_CPU(uc, mycpu)->env) & 0x1ff; + break; } } } @@ -146,6 +149,9 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i case UC_ARM_REG_FPEXC: ARM_CPU(uc, mycpu)->env.vfp.xregs[ARM_VFP_FPEXC] = *(int32_t *)value; break; + case UC_ARM_REG_IPSR: + xpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, 0x1ff); + break; } } }