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@@ -10,6 +10,7 @@ public interface RiscvConst {
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public static final int UC_CPU_RISCV32_BASE32 = 1;
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public static final int UC_CPU_RISCV32_SIFIVE_E31 = 2;
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public static final int UC_CPU_RISCV32_SIFIVE_U34 = 3;
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public static final int UC_CPU_RISCV32_ENDING = 4;
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// RISCV64 CPU
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@@ -17,6 +18,7 @@ public interface RiscvConst {
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public static final int UC_CPU_RISCV64_BASE64 = 1;
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public static final int UC_CPU_RISCV64_SIFIVE_E51 = 2;
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public static final int UC_CPU_RISCV64_SIFIVE_U54 = 3;
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public static final int UC_CPU_RISCV64_ENDING = 4;
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// RISCV registers
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