Generate bindings

This commit is contained in:
2022-04-16 17:50:32 +02:00
parent c379d1bfe4
commit 5a79d7879c
54 changed files with 1956 additions and 1878 deletions

View File

@@ -13,6 +13,7 @@ module Riscv =
let UC_CPU_RISCV32_BASE32 = 1
let UC_CPU_RISCV32_SIFIVE_E31 = 2
let UC_CPU_RISCV32_SIFIVE_U34 = 3
let UC_CPU_RISCV32_ENDING = 4
// RISCV64 CPU
@@ -20,6 +21,7 @@ module Riscv =
let UC_CPU_RISCV64_BASE64 = 1
let UC_CPU_RISCV64_SIFIVE_E51 = 2
let UC_CPU_RISCV64_SIFIVE_U54 = 3
let UC_CPU_RISCV64_ENDING = 4
// RISCV registers