Fix long-standing mips delay slot issue
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@@ -41,14 +41,25 @@ static inline void gen_tb_start(TCGContext *tcg_ctx, TranslationBlock *tb)
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tcg_gen_ld_i32(tcg_ctx, count, tcg_ctx->cpu_env,
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offsetof(ArchCPU, neg.icount_decr.u32) -
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offsetof(ArchCPU, env));
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// Unicorn:
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// We CANT'T use brcondi_i32 here or we will fail liveness analysis
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// because it marks the end of BB
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if (tcg_ctx->delay_slot_flag != NULL) {
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TCGv_i32 tmp = tcg_const_i32(tcg_ctx, 0);
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// dest = (c1 cond c2 ? v1 : v2)
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_GT, count, tcg_ctx->delay_slot_flag, tmp, tcg_ctx->delay_slot_flag, count);
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tcg_temp_free_i32(tcg_ctx, tmp);
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}
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tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_LT, count, 0, tcg_ctx->exitreq_label);
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tcg_temp_free_i32(tcg_ctx, count);
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}
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static inline void gen_tb_end(TCGContext *tcg_ctx, TranslationBlock *tb, int num_insns)
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{
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if (tcg_ctx->delay_slot_flag != NULL){
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tcg_temp_free_i32(tcg_ctx, tcg_ctx->delay_slot_flag);
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}
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tcg_ctx->delay_slot_flag = NULL;
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if (tb_cflags(tb) & CF_USE_ICOUNT) {
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/* Update the num_insn immediate parameter now that we know
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* the actual insn count. */
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