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Update constants of bindings

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This commit is contained in:
Bet4
2022-02-16 20:08:17 +08:00
parent cc45585e90
commit 504b31b928
18 changed files with 309 additions and 150 deletions
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130
bindings/rust/src/mips.rs
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@@ -9,38 +9,38 @@ pub enum RegisterMIPS {
// General purpose registers
PC = 1,
GPR0 = 2,
GPR1 = 3,
GPR2 = 4,
GPR3 = 5,
GPR4 = 6,
GPR5 = 7,
GPR6 = 8,
GPR7 = 9,
GPR8 = 10,
GPR9 = 11,
GPR10 = 12,
GPR11 = 13,
GPR12 = 14,
GPR13 = 15,
GPR14 = 16,
GPR15 = 17,
GPR16 = 18,
GPR17 = 19,
GPR18 = 20,
GPR19 = 21,
GPR20 = 22,
GPR21 = 23,
GPR22 = 24,
GPR23 = 25,
GPR24 = 26,
GPR25 = 27,
GPR26 = 28,
GPR27 = 29,
GPR28 = 30,
GPR29 = 31,
GPR30 = 32,
GPR31 = 33,
R0 = 2,
R1 = 3,
R2 = 4,
R3 = 5,
R4 = 6,
R5 = 7,
R6 = 8,
R7 = 9,
R8 = 10,
R9 = 11,
R10 = 12,
R11 = 13,
R12 = 14,
R13 = 15,
R14 = 16,
R15 = 17,
R16 = 18,
R17 = 19,
R18 = 20,
R19 = 21,
R20 = 22,
R21 = 23,
R22 = 24,
R23 = 25,
R24 = 26,
R25 = 27,
R26 = 28,
R27 = 29,
R28 = 30,
R29 = 31,
R30 = 32,
R31 = 33,
// DSP registers
DSPCCOND = 34,
@@ -203,39 +203,39 @@ impl RegisterMIPS {
// (assoc) LO1 = 46,
// (assoc) LO2 = 47,
// (assoc) LO3 = 48,
pub const ZERO: RegisterMIPS = RegisterMIPS::GPR0;
pub const AT: RegisterMIPS = RegisterMIPS::GPR1;
pub const V0: RegisterMIPS = RegisterMIPS::GPR2;
pub const V1: RegisterMIPS = RegisterMIPS::GPR3;
pub const A0: RegisterMIPS = RegisterMIPS::GPR4;
pub const A1: RegisterMIPS = RegisterMIPS::GPR5;
pub const A2: RegisterMIPS = RegisterMIPS::GPR6;
pub const A3: RegisterMIPS = RegisterMIPS::GPR7;
pub const T0: RegisterMIPS = RegisterMIPS::GPR8;
pub const T1: RegisterMIPS = RegisterMIPS::GPR9;
pub const T2: RegisterMIPS = RegisterMIPS::GPR10;
pub const T3: RegisterMIPS = RegisterMIPS::GPR11;
pub const T4: RegisterMIPS = RegisterMIPS::GPR12;
pub const T5: RegisterMIPS = RegisterMIPS::GPR13;
pub const T6: RegisterMIPS = RegisterMIPS::GPR14;
pub const T7: RegisterMIPS = RegisterMIPS::GPR15;
pub const S0: RegisterMIPS = RegisterMIPS::GPR16;
pub const S1: RegisterMIPS = RegisterMIPS::GPR17;
pub const S2: RegisterMIPS = RegisterMIPS::GPR18;
pub const S3: RegisterMIPS = RegisterMIPS::GPR19;
pub const S4: RegisterMIPS = RegisterMIPS::GPR20;
pub const S5: RegisterMIPS = RegisterMIPS::GPR21;
pub const S6: RegisterMIPS = RegisterMIPS::GPR22;
pub const S7: RegisterMIPS = RegisterMIPS::GPR23;
pub const T8: RegisterMIPS = RegisterMIPS::GPR24;
pub const T9: RegisterMIPS = RegisterMIPS::GPR25;
pub const K0: RegisterMIPS = RegisterMIPS::GPR26;
pub const K1: RegisterMIPS = RegisterMIPS::GPR27;
pub const GP: RegisterMIPS = RegisterMIPS::GPR28;
pub const SP: RegisterMIPS = RegisterMIPS::GPR29;
pub const FP: RegisterMIPS = RegisterMIPS::GPR30;
pub const S8: RegisterMIPS = RegisterMIPS::GPR30;
pub const RA: RegisterMIPS = RegisterMIPS::GPR31;
pub const ZERO: RegisterMIPS = RegisterMIPS::R0;
pub const AT: RegisterMIPS = RegisterMIPS::R1;
pub const V0: RegisterMIPS = RegisterMIPS::R2;
pub const V1: RegisterMIPS = RegisterMIPS::R3;
pub const A0: RegisterMIPS = RegisterMIPS::R4;
pub const A1: RegisterMIPS = RegisterMIPS::R5;
pub const A2: RegisterMIPS = RegisterMIPS::R6;
pub const A3: RegisterMIPS = RegisterMIPS::R7;
pub const T0: RegisterMIPS = RegisterMIPS::R8;
pub const T1: RegisterMIPS = RegisterMIPS::R9;
pub const T2: RegisterMIPS = RegisterMIPS::R10;
pub const T3: RegisterMIPS = RegisterMIPS::R11;
pub const T4: RegisterMIPS = RegisterMIPS::R12;
pub const T5: RegisterMIPS = RegisterMIPS::R13;
pub const T6: RegisterMIPS = RegisterMIPS::R14;
pub const T7: RegisterMIPS = RegisterMIPS::R15;
pub const S0: RegisterMIPS = RegisterMIPS::R16;
pub const S1: RegisterMIPS = RegisterMIPS::R17;
pub const S2: RegisterMIPS = RegisterMIPS::R18;
pub const S3: RegisterMIPS = RegisterMIPS::R19;
pub const S4: RegisterMIPS = RegisterMIPS::R20;
pub const S5: RegisterMIPS = RegisterMIPS::R21;
pub const S6: RegisterMIPS = RegisterMIPS::R22;
pub const S7: RegisterMIPS = RegisterMIPS::R23;
pub const T8: RegisterMIPS = RegisterMIPS::R24;
pub const T9: RegisterMIPS = RegisterMIPS::R25;
pub const K0: RegisterMIPS = RegisterMIPS::R26;
pub const K1: RegisterMIPS = RegisterMIPS::R27;
pub const GP: RegisterMIPS = RegisterMIPS::R28;
pub const SP: RegisterMIPS = RegisterMIPS::R29;
pub const FP: RegisterMIPS = RegisterMIPS::R30;
pub const S8: RegisterMIPS = RegisterMIPS::R30;
pub const RA: RegisterMIPS = RegisterMIPS::R31;
pub const HI0: RegisterMIPS = RegisterMIPS::AC0;
pub const HI1: RegisterMIPS = RegisterMIPS::AC1;
pub const HI2: RegisterMIPS = RegisterMIPS::AC2;