fix x86 segment setup by updating cached segment registers on reg_write
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@@ -2556,7 +2556,6 @@ void helper_verw(CPUX86State *env, target_ulong selector1)
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CC_SRC = eflags | CC_Z;
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}
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#if defined(CONFIG_USER_ONLY)
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void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)
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{
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if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
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@@ -2570,7 +2569,6 @@ void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)
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helper_load_seg(env, seg_reg, selector);
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}
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}
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#endif
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/* check if Port I/O is allowed in TSS */
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static inline void check_io(CPUX86State *env, int addr, int size)
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