Sync pc before memory hooks
This ensures correct PC for any arch
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@@ -545,9 +545,6 @@ static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (HOOK_EXISTS(s->uc, UC_HOOK_MEM_READ))
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gen_sync_pc(tcg_ctx, s->prev_pc); // Unicorn: sync EIP
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tcg_gen_qemu_ld_tl(tcg_ctx, t0, a0, s->mem_index, idx | MO_LE);
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}
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@@ -555,9 +552,6 @@ static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (HOOK_EXISTS(s->uc, UC_HOOK_MEM_WRITE))
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gen_sync_pc(tcg_ctx, s->prev_pc); // Unicorn: sync EIP
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tcg_gen_qemu_st_tl(tcg_ctx, t0, a0, s->mem_index, idx | MO_LE);
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}
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@@ -2914,9 +2908,6 @@ static inline void gen_ldq_env_A0(DisasContext *s, int offset)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (HOOK_EXISTS(s->uc, UC_HOOK_MEM_READ))
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gen_sync_pc(tcg_ctx, s->prev_pc); // Unicorn: sync EIP
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tcg_gen_qemu_ld_i64(tcg_ctx, s->tmp1_i64, s->A0, s->mem_index, MO_LEQ);
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tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset);
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}
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@@ -2925,9 +2916,6 @@ static inline void gen_stq_env_A0(DisasContext *s, int offset)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (HOOK_EXISTS(s->uc, UC_HOOK_MEM_WRITE))
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gen_sync_pc(tcg_ctx, s->prev_pc); // Unicorn: sync EIP
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tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset);
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tcg_gen_qemu_st_i64(tcg_ctx, s->tmp1_i64, s->A0, s->mem_index, MO_LEQ);
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}
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@@ -2937,9 +2925,6 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int mem_index = s->mem_index;
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if (HOOK_EXISTS(s->uc, UC_HOOK_MEM_READ))
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gen_sync_pc(tcg_ctx, s->prev_pc); // Unicorn: sync EIP
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tcg_gen_qemu_ld_i64(tcg_ctx, s->tmp1_i64, s->A0, mem_index, MO_LEQ);
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tcg_gen_st_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
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tcg_gen_addi_tl(tcg_ctx, s->tmp0, s->A0, 8);
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@@ -2952,9 +2937,6 @@ static inline void gen_sto_env_A0(DisasContext *s, int offset)
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int mem_index = s->mem_index;
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if (HOOK_EXISTS(s->uc, UC_HOOK_MEM_WRITE))
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gen_sync_pc(tcg_ctx, s->prev_pc); // Unicorn: sync EIP
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tcg_gen_ld_i64(tcg_ctx, s->tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
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tcg_gen_qemu_st_i64(tcg_ctx, s->tmp1_i64, s->A0, mem_index, MO_LEQ);
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tcg_gen_addi_tl(tcg_ctx, s->tmp0, s->A0, 8);
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